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Pipelining in Computer Architecture Question & Answers

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This Article lists 50+ Pipelining in Computer Architecture MCQs for engineering students. All the Pipelining in Computer Architecture Questions & Answers given below includes solutions and links wherever possible to the relevant topic.

In microprocessors to speed up the number of instructions per cycle various methods are used. One among such methods is Pipelining. Using pipelining in a programming language, one instruction per cycle can be executed. Depending upon hardware, different types of processors apply different stages of the pipeline.

There are 3 stages of pipelining, 4 stages, and 5 stages of pipelining. Instructions are executed in different stages such as fetch, decode, execute. In pipelining, these phases of more than one instruction are executed concurrently. Pipelining practices the concept of Parallelism.

Although pipelining increases the speed of execution, it also causes some hazards. As not all instructions can undergo parallelism, when such instructions are moved to pipelining, they stall the operation. When branch instructions are executed using pipelining they cause Read after Write pipelining hazard.

1). Pipelining is a ------------technique?
HintIt is a simultaneous operation.
2). Each stage of instruction should execute in ---------cycles?
HintIt executes in a single stage.
3). The initial stage for an instruction executing in pipelining is -----?
HintIt is used to describe a transfer
4). For a six-stage pipelining, the initial instruction requires-------cycle for execution?
HintIn this pipelining, stages depends on cycles.
5). Parallelism can be achieved by-----------technique.
HintIt depends on the hardware unit, computer software, etc.
6). To exploit Pipelining in computer architecture-----?
HintNumber of processors are used.
7). In a pipelined processor, the processing units for integers and floating point is-------?
HintIt includes an individual unit.
8). In---pipelining processor should pass the instructions through all the phases, regardless of the requirement of the requirements of instruction?
HintIt performs a single operation.
9). In -----pipeline processor, instructions not only bypass the phases but also choose then out of order?
HintThese pipelines have the capacity to schedule in the region of stalls.
10). ARM processors are available in the form of -------- pipelining?
HintIt is available in both stages.
Please refer to this link to know more about ARM Processor
11). The stages of 3 stage pipelining are----?
HintThis cycle is also called as instruction cycle.
12).---------instructions can cause a pipelining Hazard?
HintThey are RAW, Interrupt, etc.
13). Throughput is calculated as----
HintBased on the instructions or time taken to finish this task.
14). To hold the results of intermediate stages in pipelining --------are used?
HintIt stores the data temporarily.
15). 3 stage pipelining has ----- cycle latency?
HintIts cycle latency mainly depends on its stages.
16). By using pipelining, the latency of the instructions---?
HintThe instructions latency is reduced.
17). By using pipelining, the throughput of the processor----?
HintThe processor throughput will be enhanced.
18). In pipelining. each stage is given------time for the operation?
HintEvery stage gives equal time for its operation.
19). Step to be taken when a hazard occurs ------?
HintFlush and freeze the pipeline.
20). In pipelining, instructions are executed----?
HintInstructions are executed at the same time.
21). When the data operands are not available then it is called----?
HintWhen the data is not available at destination then it occurs
22). In pipelining, which of the following operation is used to enhance the memory access speed?
HintIt is not a permanent memory.
23). For pipelined systems, which of the following is particularly developed?
HintA compiler that reduces or increases some attributes in a computer program
24). The pipeline process is a…?
HintThis operation can be performed at assembly level.
25). Which of the following is used to interleave both the fetch & execution cycles?
HintThe interleaving can be performed by using a CLK.

Pipelining in Computer Architecture MCQs for Interviews

26). Types of pipelines are….?
HintThey are arithmetic & instruction.
27). What is the function of an arithmetic pipeline?
HintGenerally, these are found in computers.
28). Which of the below is not a pipeline conflicts?
HintIt is an efficient network distribution.
29). The algorithm like Tomasulo is developed in ….year?
HintIt is an efficient network distribution.
30). The Tomasulo algorithm is a hardware algorithm developed in…year?
HintThis algorithm was invented by “Robert Tomasulo” from IBM.
31). How many parts are used for addition & subtraction of floating point in arithmetic pipeline?
HintThey are Compare, Align, Add or subtract & Produce.
32). Which of the following pipeline type deals with both register, memory operands & destinations?
HintIt is a complex instruction set computer.
33). Which of the following units are called floating point units?
HintThese units are pipelined completely.
34). When pipelining increases then throughput of the processor will be…?
HintWhen processor throughput increases, it also increases.
35). Which of the following statement is not true for pipelining?
HintFor a separate instruction, it decreases the instruction time.
36). Hazards occurred in the pipelining are….types?
HintThe types are structural, data & control
37). An alternate name of pipeline stalling is called as?
HintIt delays th.e instruction processing
38). Once the instructions within pipeline are discarded then it is called as?
HintIt is also known as pipeline stall/ pipeline break
39). Control hazard is also called as?
HintThe proper instruction finding takes some time to fetch.
40). In pipelined processor, the WB stage in instruction execution is ….stage?
HintThis is a register write back stage.
41). Which of the following instruction is not used for changing state….?
HintThis instruction does nothing throughout execution.
42). Which of the following is used to implement an instruction pipeline?
HintIt is a read or write memory array
43). The best algorithm used for pipelining is…?
HintIt is a general-purpose and efficient sorting algorithm.
44). When the gained speed through an ‘n’ segment pipeline to execute task ‘m’ is…..?
HintIn non pipeline, time taken is (Twp) = no. of stages X no. of instructions = n.m. Similarly, for pipeline it is Tp = n-m+1. So, S = Twp/(n-m+1).
45). Pipelining invented in …year?
HintIt is used in supercomputers like array & ve.ctor processors
46). Once the structural hazard is resolved then the processor working turns into…..?
HintThe processor performance mainly depends on the structural hazard.
47). Pipelining decreases an…..time?
HintThis is also called runtime.
48). Once the cache is divided into separate instruction then it is called….buffer?
HintThis buffer includes a shift register.
49) .Exceptions which take place in instructions are…?
HintThese are not asynchronous.
50). When the instruction moves from one stage to other in pipeline is called…?
HintHere the two stages are decode and execution.

Pipelining in Computer Architecture MCQs for Exams

51). How many ways are used to execute the instructions in a programme…?
HintThe methods are pipelined and nonpipelined.
52). In non-pipelined execution, how the program instructions are executed?
HintProgram instructions are executed one afte.r another
53). In pipelined execution, how the instructions are executed within program?
HintSeveral instructions are executed not serially.
54). How the computer architecture is abstracted?
HintIt is a set of commands within machine language for a CPU .
55). Pipelining….the time of CLK cycle ?
HintThe CLK cycle time can be reduced by the pipelining process.
56). In which of the following pipeline, all the tasks includes equivalent processing time ?
HintIn this type, all the stages use similar time to finish the task.
57). For arithmetic logic functions, which of the following contains several functional pipelines?
HintIt is a part in CPU.
58). In pipelines, which of the following Hazard can be caused through resource conflicts?
HintThis hazard mainly occurs once two or many instructions that are previously in pipeline require the similar resource.
59). Which of the following hazards arise from the branches of pipelining?
HintThis is also called branch hazard.
60). Which of the following is not used within super scalar processing?
HintIt is a method where many instructions are overlapped throughout execution.
61). Pipeline processors are classified by …..?
HintThese processors are classified in the year 1977.
62). Pipeline processors are classified into …types based on their function?
HintThey are arithmetic, instruction, processor, unifunction and static.
63). Which of the following pipeline processor is used to perform high speed floating point addition, division & multiplication?
HintThe examples of this pipeline processor are TI-ASC, Star-100, Cyber-205 & Cray-1.
64). Which of the following pipelining is called instruction lookahead?
HintIn this type, several instructions are pipelined .
65). When the processors are pipelined for processing the similar data stream?
HintThe processing of data stream can be done through the first processor & the final result can be stored within the memory block.
66). Which of the following pipelining is used to process the instructions through scalar operands?
HintThis pipelining processor uses scalar operands.
67). The…….pipeline is used to perform a fixed-function every time?
HintThis pipeline is unifunctional.
68). Which type of pipeline is used to execute the similar type of instructions constantly?
HintIt performs fixed function every time.
69). The pipeline used to perform the exact function each time?
HintEvery time, this pipeline performs exact function.
70). Pipelining hazards are classified into …types?
HintData dependency, resource limitation, memory & branch delay .
71). Pipelining separates the instruction in ….. Stages?
HintThey are instruction fetch, decode, execution, operand fetch & store.
72). When a pipelining includes four phases like 40, 60, 30 & 70 ns duration with 10 ns latch delay, then calculate pipeline cycle time?
HintCycle time = Maximum delay because of any stage + Delay because of its register = Max { 40, 60, 30, 70 } + 10 ns = 70 +10 = 80ns
73). When a pipelining includes four phases like 50, 70, 90 & 100 ns duration with 10 ns latch delay, then calculate Non-Pipeline Execution Time?
HintFor one instruction, the Non-pipeline execution time is = 50 + 70 + 90 + 100 = 310.
74). When a pipelining includes four phases like 50, 70, 90 & 100 ns duration with 10 ns latch delay, then calculate speed up ratio?
HintFor speed up ratio = Non-pipeline execution time / Pipeline execution time = 310/100 = 3.1
75). In the following instruction pipeline, four stages are available with combinational circuit like S1, S2, S3 and S4 only. So, the pipeline registers are necessary between every phase & at the final stage end. So what is the non-pipeline execution time?
Instruction Pipeline

Instruction Pipeline

Add description here!
HintNon-pipeline execution time for single instruction = 5 ns + 6 ns + 11 ns + 8 ns = 30 ns.

Pipelining in Computer Architecture Quiz Questions

76). Pipelining strategy is used to implement…?
HintIt is used in microprocessors for speed up the program execution through decreasing wait states..
77). Data hazards takes place when ….?
HintPipeline modifies the access of read or write order to operands.
78). In pipeline hazards, pipeline stall is called…?
HintIn this, conditions do not allow nonstop execution.
79). When two or more instructions are already within the pipeline require the similar resource, then this hazard is called…..?
HintThis type of hazard is known as structural hazard.
80). Once two instructions within a program are executed in series then that is called…?
HintIn this type, an instruction mainly depends on the previous instruction’s result.
81).Data hazards are classified into…type?
HintThe types are; read after write, write after read & write after write.
82).The structural hazard is also called as…?
HintThis hazard occurs once the pipeline necessary for an instruction is not available because of a prior instruction.
83). Control hazard is also called….?
HintThis hazard occurs once the pipeline makes the incorrect decision on a prediction of branch..
84).Which pipeline reads the instructions using the memory?
HintIn this type of pipelining, set of instructions can be executed..
85).Which processor works on simple instruction….?
HintIt is a normal processor.
Please refer to this link to know more about Microprocessor
86). Which processor pipelines the data by not only using Instruction pipeline…?
HintThis processor works on multiple data all at once..
87). Superscalar processors are invented in ….year?
HintThe invention of this processor can be done in between 1985 to 1989.
88). Which processor is used to enhance the performance of scalar processor?
HintThis processor is invented in 1987.
89). Which processor executes instructions separately in dissimilar pipelines?
HintIt enhances the instructions processing..
90). which of the following processor uses one or two data items?
HintIt signifies a group of computer processors..
91).The multiple data items used by the processor is?
Hint This processor uses instruction pipeline.
92). The performance of scalar processors as compared to superscalar processors is?
HintIts performance is not faster.
93).The throughput of the system can be enhanced through…process?
HintThis is used in computer architectures.
94). In which of the following, a new instruction in each clock cycle completes its execution?
HintIn computing it is also called as a data pipeline
95).Pipelining also used to reduce….?
HintThe time taken to finish a task.
96). Which pipeline allows simply streamline connections…?
HintThese are static pipelines.
97). Dynamic pipelines are…..?
HintThese pipelines are reconfigured for performing variable tasks.
98). Generally, pipelined CPUs work at a high CLK frequency than…?
HintIt is a computer memory.
99). In a pipelined architecture with 4- stages, each instruction execution can be finished in …stages?
HintThey are IF, ID, IE & WB.
100). The pipeline included in the RISC processor has ….stages?
HintThey are IF, ID, IE, MA & WB
Please refer to this link to know more about RISC 

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