Pipelining in Computer Architecture Question & Answers November 15, 2021 By WatElectronics This Article lists 50+ Pipelining in Computer Architecture MCQs for engineering students. All the Pipelining in Computer Architecture Questions & Answers given below includes solutions and links wherever possible to the relevant topic. In microprocessors to speed up the number of instructions per cycle various methods are used. One among such methods is Pipelining. Using pipelining in a programming language, one instruction per cycle can be executed. Depending upon hardware, different types of processors apply different stages of the pipeline. There are 3 stages of pipelining, 4 stages, and 5 stages of pipelining. Instructions are executed in different stages such as fetch, decode, execute. In pipelining, these phases of more than one instruction are executed concurrently. Pipelining practices the concept of Parallelism. Although pipelining increases the speed of execution, it also causes some hazards. As not all instructions can undergo parallelism, when such instructions are moved to pipelining, they stall the operation. When branch instructions are executed using pipelining they cause Read after Write pipelining hazard. 1). Pipelining is a ------------technique? Serial operation Parallel operation Scalar operation Superscalar operation Hint 2). Each stage of instruction should execute in ---------cycles? 1 2 3 4 Hint 3). The initial stage for an instruction executing in pipelining is -----? Decode Execute Fetch Address generation. Hint 4). For a six-stage pipelining, the initial instruction requires-------cycle for execution? 1 cycle 3 cycle 6 cycle 7 cycle. Hint 5). Parallelism can be achieved by-----------technique. Hardware Compiler Software All of the above Hint 6). To exploit Pipelining in computer architecture-----? A single processor is used. The double processor is used. Multiple processors are used. None of the above. Hint 7). In a pipelined processor, the processing units for integers and floating point is-------? Same unit. Separate unit. No unit. Within each other. Hint 8). In---pipelining processor should pass the instructions through all the phases, regardless of the requirement of the requirements of instruction? Static Dynamic Complex Dynamic Both b and c Hint 9). In -----pipeline processor, instructions not only bypass the phases but also choose then out of order? Static Dynamic Complex Dynamic Both a and c. Hint 10). ARM processors are available in the form of -------- pipelining? 3 stage 5 stage Both a and b None of the above. Hint Please refer to this link to know more about ARM Processor 11). The stages of 3 stage pipelining are----? Fetch, Decode, Execute Decode, Fetch, Execute Execute, Fetch, Decode Address generation, Fetch, Execute. Hint 12).---------instructions can cause a pipelining Hazard? Branch Interrupt Read after Write All of the above Hint 13). Throughput is calculated as---- The number of instructions/ Total time to complete the instructions Total time to complete the instructions/number of instructions Speed of the processor/ Number of instructions The number of instructions/speed of the processor Hint 14). To hold the results of intermediate stages in pipelining --------are used? Caches Buffers Memory RAM units Hint 15). 3 stage pipelining has ----- cycle latency? 1 2 3 4 Hint 16). By using pipelining, the latency of the instructions---? Increases Remains the same Decreases It is unity Hint 17). By using pipelining, the throughput of the processor----? Increases becomes unity Decreases Remains the same. Hint 18). In pipelining. each stage is given------time for the operation? Equal Different Infinite None of the above. Hint 19). Step to be taken when a hazard occurs ------? Flush the pipeline Freeze the pipeline Break the pipeline Both a and b. Hint 20). In pipelining, instructions are executed----? Serially Parallel Concurrently None of the above. Hint 21). When the data operands are not available then it is called----? Deadlock Push Pop Data hazard Hint 22). In pipelining, which of the following operation is used to enhance the memory access speed? Registers Cache Stack Queue Hint 23). For pipelined systems, which of the following is particularly developed? Registers Cache Stack Queue Hint 24). The pipeline process is a…? Stack operation Queue operation Assembly line Super scalar Hint 25). Which of the following is used to interleave both the fetch & execution cycles? Memory Stack Clock Register Hint Pipelining in Computer Architecture MCQs for Interviews 26). Types of pipelines are….? 2 3 4 5 Hint 27). What is the function of an arithmetic pipeline? Addition operation Character operations Floating points Division Hint 28). Which of the below is not a pipeline conflicts? Balancing of load Character operations Time changes Dependency on data Hint 29). The algorithm like Tomasulo is developed in ….year? Balancing of load Character operations Time changes Dependency on data Hint 30). The Tomasulo algorithm is a hardware algorithm developed in…year? 1959 1962 1967 1983 Hint 31). How many parts are used for addition & subtraction of floating point in arithmetic pipeline? 2 3 4 6 Hint 32). Which of the following pipeline type deals with both register, memory operands & destinations? RISC Processor CISC Instruction Hint 33). Which of the following units are called floating point units? Vector load Vector store Vector functional Control unit Hint 34). When pipelining increases then throughput of the processor will be…? Increased Decreased Stable Slightly increased Hint 35). Which of the following statement is not true for pipelining? It decreases the execution time for an instruction It enhances the execution time for an instruction It enhances the throughput of a CPU instruction It decreases the throughput of a CPU instruction Hint 36). Hazards occurred in the pipelining are….types? 2 3 4 5 Hint 37). An alternate name of pipeline stalling is called as? Hazards Bubble Deadlock Execution Hint 38). Once the instructions within pipeline are discarded then it is called as? Encoder Decoder Flushing Deadloack Hint 39). Control hazard is also called as? Call hazard Branch hazard Data hazard Structural hazard Hint 40). In pipelined processor, the WB stage in instruction execution is ….stage? First Third Fifth Seventh Hint 41). Which of the following instruction is not used for changing state….? nope no-op nop no Hint 42). Which of the following is used to implement an instruction pipeline? FIFO LIFO Deadlock Stack Hint 43). The best algorithm used for pipelining is…? Harsh Small Quick sort Merge sort Hint 44). When the gained speed through an ‘n’ segment pipeline to execute task ‘m’ is…..? (n+m-1)/mn (n-m+1)/m+n mn/(n+m-1) (n-m+1)/mn Hint 45). Pipelining invented in …year? 1965 1970 1978 1980 Hint 46). Once the structural hazard is resolved then the processor working turns into…..? Slower Faster Stable Large Hint 47). Pipelining decreases an…..time? Execution Resuming Terminating Cycle Hint 48). Once the cache is divided into separate instruction then it is called….buffer? Instruction Data Terminating Cache Hint 49) .Exceptions which take place in instructions are…? Blocked Synchronous Pipelined Asynchronous Hint 50). When the instruction moves from one stage to other in pipeline is called…? Instruction issue Deadlock Compiling Nullifying Hint Pipelining in Computer Architecture MCQs for Exams 51). How many ways are used to execute the instructions in a programme…? 2 3 4 5 Hint 52). In non-pipelined execution, how the program instructions are executed? Sequentially Parallel Alternatively None of the above Hint 53). In pipelined execution, how the instructions are executed within program? Sequentially Parallely Alternatively Not serially Hint 54). How the computer architecture is abstracted? Through memory Through instruction set Through instruction only Through organization Hint 55). Pipelining….the time of CLK cycle ? Increases Decreases No change Slightly increases Hint 56). In which of the following pipeline, all the tasks includes equivalent processing time ? Instruction Uniform Delay Processor Arithmetic Hint 57). For arithmetic logic functions, which of the following contains several functional pipelines? Instruction Unit Execution unit Uniform Delay Instruction queue Hint 58). In pipelines, which of the following Hazard can be caused through resource conflicts? Control Structural Data RAW Hint 59). Which of the following hazards arise from the branches of pipelining? Control RAW Data Structural Hint 60). Which of the following is not used within super scalar processing? Serial instruction Parallel decoding Pipelines Parallel encoding Hint 61). Pipeline processors are classified by …..? Handler & Ramamoorthy John Von Gerrit Blauuw Stanley Williums Hint 62). Pipeline processors are classified into …types based on their function? 2 4 6 8 Hint 63). Which of the following pipeline processor is used to perform high speed floating point addition, division & multiplication? Arithmetic Processor Unifunction Static Hint 64). Which of the following pipelining is called instruction lookahead? Arithmetic Static Processor Instruction Hint 65). When the processors are pipelined for processing the similar data stream? Instruction Processor Arithmetic Static Hint 66). Which of the following pipelining is used to process the instructions through scalar operands? Instruction Scalar Static Arithmetic Hint 67). The…….pipeline is used to perform a fixed-function every time? Instruction Scalar Static Arithmetic Hint 68). Which type of pipeline is used to execute the similar type of instructions constantly? Arithmetic Static Instruction Scalar Hint 69). The pipeline used to perform the exact function each time? Unifunction Scalar Static Instruction Hint 70). Pipelining hazards are classified into …types? 2 3 4 5 Hint 71). Pipelining separates the instruction in ….. Stages? 2 3 4 5 Hint 72). When a pipelining includes four phases like 40, 60, 30 & 70 ns duration with 10 ns latch delay, then calculate pipeline cycle time? 70 80 90 100 Hint 73). When a pipelining includes four phases like 50, 70, 90 & 100 ns duration with 10 ns latch delay, then calculate Non-Pipeline Execution Time? 250 300 310 320 Hint 74). When a pipelining includes four phases like 50, 70, 90 & 100 ns duration with 10 ns latch delay, then calculate speed up ratio? 3.5 3.1 2.8 2.7 Hint 75). In the following instruction pipeline, four stages are available with combinational circuit like S1, S2, S3 and S4 only. So, the pipeline registers are necessary between every phase & at the final stage end. So what is the non-pipeline execution time? Instruction Pipeline Add description here! 20 ns 25 ns 30 ns 35 ns Hint Pipelining in Computer Architecture Quiz Questions 76). Pipelining strategy is used to implement…? Instruction execution Instruction manipulation Instruction prefetch Instruction decoding Hint 77). Data hazards takes place when ….? Performance loss is huge Read/Write order changes to operands Functional unit is not completely pipelined Limited machine size Hint 78). In pipeline hazards, pipeline stall is called…? Pipeline bubble Pipeline Unit Pipeline execution Instruction manipulation Hint 79). When two or more instructions are already within the pipeline require the similar resource, then this hazard is called…..? Resource Hazard Pipeline Hazard Control Hazard Data Hazard Hint 80). Once two instructions within a program are executed in series then that is called…? Data Hazard Resource Hazard Control Hazard Pipeline Hazard Hint 81).Data hazards are classified into…type? 2 3 4 5 Hint 82).The structural hazard is also called as…? Pipeline Hazard Control Hazard Data Hazard Resource Hazard Hint 83). Control hazard is also called….? Pipeline Hazard Control Hazard Branch hazard Resource Hazard Hint 84).Which pipeline reads the instructions using the memory? Arithmetic Processor Instruction Vector Hint 85).Which processor works on simple instruction….? Super scalar Scalar Pipelined Vector Hint Please refer to this link to know more about Microprocessor 86). Which processor pipelines the data by not only using Instruction pipeline…? Scalar Super scalar Vector Pipelined Hint 87). Superscalar processors are invented in ….year? 1980 1985 1987 1989 Hint 88). Which processor is used to enhance the performance of scalar processor? Pipelined Scalar Vector Super scalar Hint 89). Which processor executes instructions separately in dissimilar pipelines? Scalar Super scalar Vector Pipelined Hint 90). which of the following processor uses one or two data items? Scalar Super scalar Vector Pipelined Hint 91).The multiple data items used by the processor is? Scalar Vector Pipelined Super scalar Hint 92). The performance of scalar processors as compared to superscalar processors is? Slower Faster Much faster Very slower Hint 93).The throughput of the system can be enhanced through…process? Pipelining Sorting Hazard Fetching Hint 94). In which of the following, a new instruction in each clock cycle completes its execution? Fetching Hazard Pipelining Sorting Hint 95).Pipelining also used to reduce….? Cycle time Sorting Performance Memory Hint 96). Which pipeline allows simply streamline connections…? Arithmetic Instruction Vector Linear pipeline Hint 97). Dynamic pipelines are…..? Non-Linear pipeline Vector Instruction Linear pipeline Hint 98). Generally, pipelined CPUs work at a high CLK frequency than…? RAM CLK frequency ROM Instruction Speed Hint 99). In a pipelined architecture with 4- stages, each instruction execution can be finished in …stages? 4 6 8 16 Hint 100). The pipeline included in the RISC processor has ….stages? 4 6 5 16 Hint Please refer to this link to know more about RISC Time is Up! Time's up
