100+ Physical Design VLSI MCQs with Answers

Physical Design (PD) is one of the most critical and challenging stages in the VLSI design flow, bridging the gap between logical design and silicon fabrication. While RTL design and synthesis focus on what the circuit should do, physical design determines how well it will work on silicon in
terms of performance, power, and area (PPA).

The following MCQs on Physical Design are carefully curated to test not just theoretical knowledge, but also practical understanding, tool-oriented thinking, and interview-level reasoning. The questions progress from intermediate to advanced difficulty, covering real-world concepts such as placement congestion, CTS skew, routing challenges, timing corners, signal integrity, power integrity, and signoff checks. Each MCQ is accompanied by a hint and explanation, making this collection ideal for:

VLSI students and fresh graduates
ASIC / SoC interview preparation
GATE and competitive exam aspirants
Engineers revising core PD concepts

These MCQs are designed to reflect how Physical Design is actually practiced in the industry—where trade-offs, constraints, and corner cases matter as much as textbook definitions.

1). What is the primary objective of Physical Design in VLSI?

RTL verification

Functional correctness

Convert netlist into manufacturable layout

Power estimation

2). Which file is the direct input to Physical Design?

RTL

Behavioral model

Synthesized netlist

GDSII

3). What is the final output of Physical Design?

Netlist

Timing report

DEF

GDSII

4). Which step comes first in the PD flow?

Clock Tree Synthesis

Placement

Floorplanning

Routing

5). What does core utilization represent?

Die area usage

Routing congestion

Percentage of core occupied by cells

Power efficiency

6). Why are macros placed first during floorplanning?

They are faster

They are movable later

They are fixed-size blocks

They consume less power

7). What happens if core utilization is too high?

Lower power

Routing congestion

Better timing

Smaller die size

8). Which layer is usually used for power routing?

Poly

Metal1

Upper metal layers

Diffusion

9). What is IR drop?

Clock skew

Signal delay

Voltage drop in power network

Crosstalk noise

10). Why is power planning done before placement?

To reduce leakage

To fix routing

To ensure stable voltage delivery

To reduce die size

11). What is the goal of placement?

Route signals

Place cells legally and optimally

Insert buffers

Fix timing

12). What does “legal placement” mean?

Timing-optimized placement

Power-optimized placement

No overlaps and aligned to rows

Routed placement

13). Which placement step optimizes timing and congestion?

Global placement

Detailed placement

Clock placement

Floorplanning

14). What is cell spreading used for?

Reduce power

Increase utilization

Reduce congestion

Reduce leakage

15). Which factor does NOT directly affect placement quality?

Wirelength

Timing

Congestion

RTL coding style

16. What is the main goal of CTS?

Reduce power

Minimize clock skew

Reduce area

Improve routability

17). What is clock skew?

Delay of data path

Difference in clock arrival times

Clock frequency variation

Jitter

18). What is useful skew?

Unavoidable skew

Skew added intentionally to improve timing

Skew due to routing

Negative skew only

19). Which elements are inserted during CTS?

Standard cells

Clock buffers and inverters

Power switches

Fill cells

20). Why is CTS done after placement?

To save power

To know exact cell locations

To reduce routing

To improve utilization

21). What is global routing?

Exact wire routing

Routing estimation

Clock routing

Power routing

22). What is detailed routing?

Congestion analysis

Track assignment

Exact geometry routing

Timing analysis

23). What causes routing congestion?

Low utilization

Excess whitespace

High pin density

Larger die

24). What is antenna effect?

Clock noise

Accumulated charge during fabrication

Crosstalk

IR drop

25). How is antenna violation fixed?

Buffer insertion

Diode insertion

Gate resizing

Re-floorplanning

Physical Design VLSI MCQs for Interviews

26). What is Static Timing Analysis (STA)?

Simulation-based timing

Vector-dependent timing

Vectorless timing analysis

Functional verification

27). What is setup violation?

Data arrives too late

Data arrives too early

Clock arrives late

Power glitch

28). What is hold violation?

Data arrives too late

Data arrives too early

Clock skew only

IR drop

29). Which stage mostly affects hold timing?

Floorplanning

Placement

CTS

Routing

30). How are hold violations usually fixed?

Reduce clock frequency

Add delay buffers

Increase voltage

Reduce die size

31). What is dynamic power mainly dependent on?

Leakage current

Switching activity

Threshold voltage

Temperature

32). What causes crosstalk?

Clock skew

Power noise

Capacitive coupling

Inductive loops

33). How can crosstalk be reduced?

Reduce spacing

Shielding

Higher utilization

Thinner wires

34). What is electromigration?

Charge accumulation

Metal atom movement due to current

Clock drift

Leakage increase

35). How is electromigration mitigated?

Reduce wire width

Increase current

Use wider metal

Lower voltage

36). What does DRC check?

Timing

Logical correctness

Manufacturing rules

Power

37). What does LVS verify?

Timing vs layout

Schematic vs layout

Power vs layout

Clock vs data

38). What is ERC?

Electrical Rule Check

Engineering Rule Check

Event Rule Check

Energy Rule Check

39). What happens if LVS fails?

Chip works slower

Layout rejected

Fabrication proceeds

Power increases

40). Which file is used for tape-out?

DEF

LEF

GDSII

Verilog

41). What is congestion-driven placement?

Power-based placement

Timing-only placement

Placement considering routing resources

Random placement

42). What is clock latency?

Clock skew

Clock insertion delay

Clock frequency

Clock jitter

43). What is negative slack?

Extra timing margin

Timing violation

Hold fix

Power issue

44). Which corner is worst for setup timing?

Fast-fast

Slow-slow

Typical

Best-case

45). Which corner is worst for hold timing?

Slow-slow

Typical

Fast-fast

Low voltage

46). Which tool is commonly used for PD?

ModelSim

PrimeTime

Innovus

Verdi

47). What does LEF contain?

Full layout

Abstract cell info

RTL

Timing only

48). What does DEF describe?

Cell library

Logical netlist

Placement and routing

Timing models

49). What is filler cell insertion for?

Timing

Power planning

DRC compliance

CTS

50). What is tap cell insertion?

Clock optimization

Power gating

Well biasing

Routing fix

Physical Design VLSI MCQs for Quiz

51).Which metric is most commonly used to estimate wirelength during placement optimization?

Steiner Tree Length

Manhattan Distance

Half-Perimeter Wire Length (HPWL)

Euclidean Distance

52). Why is very high core utilization risky in physical design?

Increases leakage power

Reduces operating voltage

Causes routing congestion

Increases clock jitter

53). What is the primary purpose of placement blockages?

Improve timing

Restrict cell placement in specific regions

Reduce power consumption

Improve CTS balance

54). Pin accessibility issues mainly impact which PD stage?

Floorplanning

Routing

CTS

Power planning

55). What is the main objective of congestion-driven placement?

Reduce clock skew

Improve power integrity

Distribute cells to reduce routing hotspots

Minimize leakage

56). Which factor is most critical while placing large macros?

Switching activity

Aspect ratio

Routing channels around macros

Clock frequency

57).What does flyline represent in PD tools?

Final routed wire

Estimated straight-line net connection

Clock routing

Power stripe

58). Which PD step usually introduces the most buffers?

Placement

CTS

Floorplanning

Power planning

59). Why are standard cells placed in rows?

Reduce power

Improve routing

Align diffusion and wells

Improve timing

60). Which routing stage assigns exact metal tracks and vias?

Global routing

Track assignment

Detailed routing

Clock routing

61). What is the main reason for inserting filler cells?

Improve timing

Reduce leakage

Maintain well and power continuity

Reduce congestion

62). Which PD artifact defines placement rows and routing tracks?

DEF

LEF

GDSII

Verilog

63). What happens if tap cells are missing?

Increased delay

Floating wells

Routing failure

Clock skew

64). What primarily determines routing congestion?

Die size

Number of metal layers

Local pin density

Clock frequency

65). Which statement about global routing is TRUE?

Produces final wires

Assigns exact vias

Estimates routing demand

Fixes DRC errors

66). What is the impact of macro halos?

Increase utilization

Improve power

Reserve routing space around macros

Improve timing

67). Which metric reflects routability during placement?

Slack

Congestion map

IR drop

Leakage

68). Which is NOT a legal placement constraint?

No overlap

Row alignment

Timing closure

Site compatibility

69). What causes detours in routing?

Extra metal layers

Routing blockages

Larger die

Lower utilization

70). Why are IO cells placed early in PD?

Improve power

Fix die boundary

Improve CTS

Reduce leakage

71). What is the role of endcap cells?

Timing optimization

Close diffusion at row ends

Reduce congestion

Power gating

72). Which factor directly affects antenna violations?

Cell density

Metal length before via

Clock skew

Leakage power

73). Which PD stage first considers timing optimization seriously?

Floorplanning

Placement

Routing

Signoff

74). What is whitespace mainly used for?

Power savings

Routing and timing optimization

Reduce area

Reduce leakage

75). Which report helps identify routing hotspots?

Timing report

Power report

Congestion report

LVS report

Physical Design VLSI MCQs for Exams

76). Which condition is worst for setup timing analysis?

Fast-Fast corner

Slow-Slow corner

Typical corner

Best-case corner

77). Which corner is most critical for hold timing?

Slow-Slow

Typical

Fast-Fast

High temperature

78). What is clock latency?

Clock skew

Clock insertion delay

Clock jitter

Clock period

79). What does negative slack indicate?

Extra margin

Timing violation

Hold fixed

Power issue

80). Why are hold fixes usually done after CTS?

CTS creates skew

Placement fixes hold

Routing removes skew

Power planning affects hold

81). What is useful skew?

Accidental skew

Skew used to fix setup timing

Skew due to routing

Negative skew only

82). What is OCV used for?

Power estimation

Delay variation modeling

Routing optimization

Clock generation

83). AOCV improves upon OCV by considering what?

Voltage

Distance of paths

Temperature

Fanout

84). What problem does shielding primarily solve?

IR drop

Crosstalk noise

Setup violation

85). Why do clock nets often use higher metal layers?

Lower capacitance

Lower resistance and EM safety

Easier routing

Better DRC

86). What is electromigration caused by?

Voltage drop

High current density

High temperature only

Crosstalk

87). How is EM risk reduced in power nets?

Narrow wires

Via reduction

Wider metals and via arrays

Lower frequency

88). What is an ECO in PD?

Full re-layout

Minor design change after signoff

Power optimization

Clock redesign

89). What does LVS failure indicate?

Timing issue

Layout vs netlist mismatch

Power issue

Congestion issue

90). Why is metal fill inserted?

Improve timing

Reduce leakage

Ensure CMP uniformity

Reduce skew

91). What is double patterning related to?

Timing

Lithography constraints

Power planning

CTS

92). What is the main risk of aggressive hold fixing?

Power increase

Area increase

Setup violation creation

IR drop

93). Why are always-on cells special?

Faster

Connected to always-on power

Used only in CTS

Reduce leakage

94). What does UPF/CPF describe?

Routing rules

Power intent

Timing constraints

Layout rules

95). Which cell is required between voltage domains?

Buffer

Isolation cell

Level shifter

Filler

96). Why are via arrays preferred on critical nets?

Save area

Reduce resistance and EM risk

Reduce capacitance

Improve CTS

97). Which PD stage has the highest impact on final PPA?

Routing

CTS

Floorplanning

Signoff

98). What does signoff timing analysis use?

Typical corner only

Best case corner

Worst-case corners

Fast corner only

99). Why is tape-out considered irreversible?

Too expensive

No simulation

Masks are generated

Power fixed

100). Physical Design success is best measured by which metric?

Area only

Performance only

Power only

Balanced PPA