VLSI Design Technology Question & AnswersJune 21, 2021 By WatElectronics This article lists 100+ VLSI Design Technology MCQs for engineering students. All the VLSI Design Technology Questions & Answers given below include a hint and wherever possible link to the relevant topic. This is helpful for the users who are preparing for their exams, interviews, or professionals who would like to brush up their fundamentals on the VLSI Design Technology topic.The components like Resistors, Capacitors, Diodes, and Transistors are manufactured separately & these are joined through wires or on a Printed Circuit Board (PCB) to form different circuits which are known as Discrete circuits. For the design of large circuits, more space is needed to accommodate multiple required components, as well as the circuit's reliability, gets affected.To overcome this issue, a circuit with various components are interconnected on a single chip has been developed that is known as an Integrated circuit.Further, the placement of the number of active devices leads to various generations in the IC technology. VLSI is a part of Integrated circuits that paved the way for various applications in the electronic industries like Image and video processing, telecommunications, consumer electronics. 1). VLSI is an acronym for _________________.Very large Scale IntegrationVarying large Scale IntegrationVarying large Scale IntegrityNone of the aboveHintNumber of transistors fabricated within a single chip 2). Integration circuits possess ______ basic generations.ThreeFourFiveSixHintSSI, MSI, LSI and VLSI 3). Integrated circuit created by VLSI due to the combination of __________ transistors.MOSUJTDiodesBoth b & cHintTo develop complex technologies like telecommunications 4). MOSFETs possess __________.Low packing densityHigh packing densityPoor packing densityNone of the aboveHintMOSFETs are widely preferred in digital circuits 5). The circuits integrated are _______ in size.LargerVery largeSmallerBulkierHintIntegrating different components on a single chip 6). Integrated chip with lesser than 10 transistors is known as _________.Small-scale integrationMedium-scale integrationLarge-scale integrationVery large-scale integrationHintSSI consists of 3-30 gates on each chip 7). How many gates are present on each chip for Medium scale integration?3-3030-300300-3000None of the aboveHintMedium-scale integrated chip consists of 30-300 gates 8). The number of transistors present in LSI are __________.Less than 1010-100100-1000Between 1000-10,000HintThousands of transistors 9). The classification of ICs is also based on _______.Number of transistors presentPresence of the active devicesBoth a & bNone of the aboveHintNumber of transistors or the other devices that are actively present 10). Which circuits work on low voltages?Integrated circuitsDiscrete circuitsBoth a and bNone of the aboveHintIntegrated circuits can be operated 11). More amount of power can be handled by _________ circuits.IntegratedDiscreteBoth a and bNone of the aboveHintMore amount of voltages and power can be handled by Discrete circuits 12). Isolation among the devices is a must in ___________ circuits.IntegratedDiscreteBoth a and bNone of the aboveHintIn discrete circuits, transistors are possible to cut individually 13). The adjoining transistors in an integrated circuit can be isolated using ___________ technique.Forward biased PN junctionOxidationMetallizationReverse biased PN junctionHintReverse-biased PN junction doesn’t allow the current to flow 14). The initial step involved in the IC fabrication is ___________.MetallizationIon implantationOxidationSilicon wafer preparationHintManufacturers of semiconductors purchase ready-made wafers of silicon 15). Wafers properties depends upon the ____________ of crystalline structures.OrientationConcentrations of impurityPresence of various impuritiesAll the aboveHintOrientation of the crystals, concentration, and the presence of impurities 16). The process in which the impurities added to the pure form of silicon is known as ____________.DopingOxidationMetallizationOrientationHintElectrical property of silicon gets altered because of Doping 17). Heavily doped silicon has _________ resistivity.HighMediumLowUltra highHintHigher properties of conduction 18). Silicon doped with Boron to obtain _________ substrate.N+ typeP+ typeN-typeP-typeHintBoron is categorized under Group three of elements 19). The resistivity of the crystal is controlled by the value of _______ added.DopantSubstrateResistanceCapacitanceHintResistivity is controlled by the amount of Dopant 20). The thickness and the size of the crystal is _________ proportional to each other.IndirectlyInverselyDirectlyNone of the aboveHintSize and the thickness of the crystal are directly proportional 21) .What is the second step in the IC fabrication?DopingOxidationMetallizationOrientationHintSilicon tends to react with oxygen and produces silicon dioxide 22). In silicon the ability of controlling the various impurities and the concentration of doping leads to the formation of _____________________.DiodesTransistorsResistorsAll the aboveHintResistors, transistors, and diodes to form in the Integrated circuits 23). What are the types of oxidation?Dry oxidationWet oxidationBoth a & bNone of the aboveHintSilicon undergoes oxidation 24). Deposition of gate oxide prefers _______.Dry oxidationWet oxidationBoth a & bNone of the aboveHintThickness of the oxidation can be controlled in dry oxidation 25). Masking oxide preparation prefers ___________.Dry oxidationWet oxidationBoth a & bNone of the aboveHintChemical and the electrical properties of the film are not criticalVLSI Design Technology MCQs for Interview 26). The silicon wafer when reacted with oxygen is converted to _________.Silicon dioxide`Silicon oxideSilicaOxygenHintConversion from silicon to sio2 27). Oxidation in silicon can be occurred by raising ______PressureHumidityTemperatureVolumeHintRaising the temperature 28). Sio2 is excellent at ____.InsulatingDielectricMaskingAll the aboveHintInsulating, Dielectric, and Masking 29). The selective removal of oxide from the crystal is known as ___________.PhotolithographyOxidationMetallizationOrientationHintThird step in processing 30). Photolithography is all about _____________.Photo resistMasksRadiationAll the aboveHintCreate detailed patterns in the material 31). For a p-type substrate the diffusion is performed with ___________.P+N+Both a & bNone of the aboveHintHeavily doped n-region 32). What is next step after Photolithography?OxidationMetallizationOrientationDiffusionHintBuried layer diffusion 33). The diffusion of n+ layer can occur by using _________ dopant.AntimonyArsenicEither a or bBoth a & bHintDiffusion performed using either antimony or arsenic 34). Growing another layer of crystal on above the top of substrate is known as _______________.DopantEpitaxyPhoto resistMaskHintPerformed after diffusion 35). The n layer formed due to epitaxy acts as __________ of an npn transistor.EmitterBaseCollectorOhmic contactHintN layer behavior resembles the collector of the NPN transistor 36). Buried layer diffusion of n+ is performed to reduce _______.Emitter resistanceBase resistanceOhmic resistanceCollector resistanceHintBuried layer forms a low resistive path 37). After all the terminals of the transistor and the ohmic contacts are formed the contact to the outer world is established by ________.Contact metallizationIon implantationOxidationDiffusionHintMetallization needs the selective depositionmetallization needs the selective deposition 38). The metal preferred in VLSI for contacting is _________.AntimonySiliconAluminumGermaniumHintGroup 3 39). In the advent of the latest technology the contact metal aluminum is replaced with _______.AntimonySiliconCopperGermaniumHintForming contact using aluminum for lightly doped regions is difficult 40). Doping can also be done by using ________.Contact metallizationIon implantationOxidationDiffusionHintMore flexibility than diffusion 41). Field oxide is the first step of fabrication in ___________.BJTUJTMOSFETCMOSHintStep of fabrication in MOSFET 42). The thickness of field oxide in the MOSFET is _________.HighMediumLowUltra highHintMOSFETs have high field oxide thickness 43). _________ takes active participation performance wise.Field oxideSilicon oxideGate oxideSubstrateHintThickness of gate oxide in the MOSFET will be less. 44). What is the most critical step in the fabrication of MOSFETs?Field oxidationSilicon oxidationGate oxideWafer preparationHintGate oxide has less thickness 45). MOSFET is a __________ device.Uni-polarBipolarComplementarySupplementaryHintMajority of carriers are responsible for the current flow 46). Types of transistors provided by CMOS technology are ____________.N-type transistorsP-type transistorsBoth a & bData insufficientHintCMOS technology produces two types of transistors 47). Different terminals of the MOS transistors are __________.SourceDrainGateAll the aboveHintFor an n-substrate, the source and the drain are doped with p+ 48).Different types of MOS layers are _______.N-diffusionP-diffusionPolysilicon and metalAll the aboveHintP-diffusion, N-diffusion, Polysilicon, and metal 49). What are the various modes in the MOSFETs?EnhancementDepletionBoth a & bNone of the aboveHint Based on the application of gate voltage and its conducting behavior the MOSFETs are classified 50). Enhancement mode MOSFETs are initially _________.OffOnCan’t sayFluctuatesHintConduct only when the gate voltage is appliedVLSI Design Technology Question & Answers 51). ___________ MOSFETs are always ON initially.EnhancementDepletionBoth a & bNone of the aboveHintDepletion MOSFETs offer conduction even though there is no initial gate voltage 52). Power is wasted in ________ MOSFETs.EnhancementDepletionBoth a & bNone of the aboveHintDepletion mode MOSFETs are initially ON 53). For Digital applications ________ is used. 53). For Digital applications ________ is used.Enhancement MOSFETsDepletion MOSFETsBoth a & bNone of the aboveHintEnhancement mode becomes conducting based on the gate voltage applied 54). Depletion mode n MOSFETs have __________ threshold voltage.PositiveNegativeZeroCan’t sayHintTo turn OFF n MOSFETs it requires a negative threshold 55). The threshold voltage of the MOSFET depends upon ________.Thickness of Gate oxideDoping concentration of substrateVariant of metal placed on GateAll the aboveHintThe gate oxide thickness, metal placed on it, and the substrates doping concentration 56). What are the various types of process in CMOS?P-well and N-wellSilicon-On-InsulatorTwin-tubAll the aboveHintIntegration of N-MOS and P-MOS transistors 57). The combination of CMOS and the bipolar technologies is ____________.Bi-CMOSInverterUPSNone of the aboveHintCombined benefits of bipolar and CMOS technologies 58).The various advantages of CMOS process are ____________.Low power dissipationHigh packing densityOffers Bidirectional capabilitiesAll the aboveHintLow amount of power dissipation with a higher density as well as a low amount of impedance 59). Transistors with lesser length of channel i.e., in between 3 to 5 microns are known as _______.BipolarUnipolarShort channel devicesLong channel devicesHintDevices are known for reducing the ratio between vertical and lateral dimensions 60). A device in a circuit connected to drag the value of the voltage at output to the lowest supply of voltage is known as ____________.Pull down devicePull up deviceShort channel deviceLong channel deviceHintPull the voltage at output usually up to 0 volts 61).Pull up devices can drag the voltage at output to __________.Zero voltsUpper supply voltageLower supply voltageNone of the aboveHintPull up the output voltages usually to VD 62). Which technology is preferred than PMOS?MOSBJTNMOSUJTHintTransistors with n-channel offer higher switching speeds 63). What are the different regions in which MOS transistors operate?Cut off regionSaturated regionNon-saturated regionAll the aboveHintThree regions 64). ____________ is acts as a interface in between the actual layout and the symbolic circuit.Pie diagramsVenn diagramsStick diagramsBoth a & bHintDiagram's purpose is to convey the information using color codes 65). Green colour in the stick diagram represents ___________.N-diffusionP-diffusionPolysiliconContactsHintN-diffusion is represented by green color 66). Red colour in the stick diagram represents __________.N-diffusionP-diffusionPolysiliconContactsHintPolysilicon 67). Buried contact is represented by _____________ colour.GreenRedYellowBrownHintRepresented by brown color 68). Contact areas in the stick diagram are represented by ________ colour.GreenBlackYellowBrownHintTaps and the contacts 69). Increase in the VDS cause growth of ___________at the junction of drain.Majority carriersMinority carriersDepletion regionInvalid dataHintGrowth of depletion region reduces the effective channel length 70). Substrate-bias effect is also known as __________.Body effectBias effectPhoto resistMass effectHintThreshold voltage varies concerning the voltage difference 71). Threshold voltage in the MOS transistor is applied in between ________ and ______ terminals.Source and DrainSource and GateGate and sourceGate and DrainHintCurrent from drain to source drops to zero 72). Time taken by the waveform to rise initially from ‘10 % to 90%’ of the steady-states value is known as __________.Rise timeFall timeDelay timeTransient responseHintRise time determines the rise in the level 73).Time taken by the waveform to fall from ‘90% to 10%’ of the steady-states value is known as _________.Rise timeFall timeDelay timeTransient responseHintFall time determines the fall in the level 74).Time taken to pass a logical transition from the input stage to the output is known as ____Rise timeFall timeDelay timeTransient responseHintDifference in time amid transitions at the input 75).What are the types involved in power dissipation?Dynamic dissipationStatic dissipationBoth a & bCan’t sayHintStatic and the dynamic dissipation'sVLSI Design Technology Important Questions with Answers 76). Leakage current results in __________ dissipation.DynamicStaticBoth a & bCan’t sayHintCurrent taken continuously from the supply 77). Dynamic dissipation occurs due to ______.Charging of capacitances at loadDischarging of capacitances at loadSwitching of transient currentsAll the aboveHintChange in the transient currents, charging, and discharging phenomena of the capacitance 78). CAD in VLSI stands for _______.Computer aided designComputer aided draftComputer animated designComplete aided designHintAbstract level description of a chip 79). BOOM is a ________.SoftwareCAD toolBoth a & bNone of the aboveHintCAD tools used in VLSI design 80). Which is the software used in VLSI?XilinxCadenceLOONBoth a & bHintLOON stands for Local Optimization of Nets 81). ____________ is used in the modeling of digital systems i.e., from algorithmic to switching.CC++VerilogJavaHintHardware descriptor language 82). How many types of modeling are present in Verilog?TwoThreeFourFiveHintThree levels of modeling 83). What are the various modeling in Verilog?Gate levelData flowBehavioralAll the aboveHintNo component type modeling 84). ___________ modeling describes the usage of logic gates and specifies the way they are wired or connected.Gate levelData flowBehavioralAll the aboveHint Gate level modeling is the structural modeling 85). _______________ modeling controls the simulations and manipulates the variables of data types.Gate levelData flowBehavioralAll the aboveHintSimulation and the manipulation required for data types 86). In Verilog X represents ___________ condition in the hardware circuits.High impedanceUnknown value of logicLogic 1Logic 0HintX is the unknown logic value 87). High impedance and the floating state in Verilog is represented by ______.ZXY1HintConditions present in hardware circuits 88). False condition in hardware is represented by ________.ZX01HintLogic zero 89). Level 1 represents ___________ in the hardware circuits.High impedanceUnknown value of logicFalse conditionTrue conditionHintLogic one 90). In which phase the micro design of the hardware gets modeled into HDL?RTL codingPlacementRoutingPost validationHint RTL coding uses a synthesize construct 91). The information about the timing of gates is present in ___________-.RegisterSynthesizerStandard delay fileFileHintFile is generated from the phase of placement and routing 92). RTL coding in the VLSI design flow comes under ________ process.Back endFront endBoth a & bNone of the aboveHintSpecification to functional verification are considered to be the front end 93). Placement and Routing in VLSI comes under ____________ VLSI design.Back endFront endBoth a & bNone of the aboveHintLogic synthesis up to Fabrication come under Back end VLSI designing 94). ASIC stands for _________.Application standard of integrated circuitsApplication-specific intercommunication circuitApplication-specific integrated circuitAmerican standard integrated circuitHintASICs are ICs customized for specific purposes 95). The prefabricated chip of silicon with the most number of transistors has no functions predetermined are known as __________.Gate arraysRegistersUncommitted logic arraysBoth a & cHintTransistors are connected by the layers of metal 96). How many types of gate arrays are present in ASIC?ThreeFourFiveSixHintThree basic gate arrays are categorized in ASICs 97). What are the methods of timing control?Delay-based timing controlEvent-based timing controlLevel-sensitive timing controlAll the aboveHintTiming controls have their specific sub-categories 98). Verilog supporting the basic form of logic gates are known as ___________.Predefined primitivesGate arraysULAsNone of the aboveHintOR, XOR, XNOR, AND, NAND, Buffer 99). What are the blocks present in Behavioral modeling?Initial blockAlways blockBoth a & bInfinite blockHintTwo blocks 100). Which block gets executed in a particular loop and during simulation gets repeated?Initial blockAlways blockBoth a & bInfinite blockHintAlways block repeats during simulation 101). What are the various types of ASIC?Full customSemi customProgrammableAll the aboveHintSemi-custom and programmable ASICS have their subcategories 102). FPGA classified under _________ ASIC.Full customSemi customProgrammableAll the aboveHintPLDs and FPGAs 103). Predesigned cells of logic used in a cell based ASIC are known as _____________Standard cellsPrimitivesArraysLogic gatesHintPlacement required for a standard cell 104). EEPROM stands for _________.Electrically Erasable Portable ROMElectrically Erasable Programmable ROMElectrically Erasable Programmable Register of MemoryElectrically Eligible Portable Register of MemoryHintPALs programming 105). Logic cells present in the library of gate arrays are known as _________.MicrosMacrosMicronsPrimitivesHintIntellectual properties 106). PALs consist of devices that are programmed by altering the switching elements characteristics are known as _______.MacrosAntifuseProgrammable interconnectsFusible linksHintTo find the paths of routing 107). _____________ tests are used in design cycle as early as possible to verify the circuit functionality.Functionality testsManufacturing testsBoth a & bNone of the aboveHintTo achieve the function desired 108). ________ tests verify each register and gate functioning properly or not.Functionality testsManufacturing testsBoth a & bNone of the aboveHintAfter the chip gets manufactured 109). Examples of Fault models __________.Stuck-at faultsShort-circuit faultsOpen-circuit faultsAll the aboveHintFault model describes how a fault occurred 110). The input of a faulty gate modeled to get stuck at zero or stuck at one is possible in ______________.Stuck-at faultsShort-circuit faultsOpen-circuit faultsAll the aboveHintMetal-to-metal or thin-oxides shorts Time is Up!