VLSI Design Technology Question & Answers June 21, 2021 By WatElectronics This article lists 100+ VLSI Design Technology MCQs for engineering students. All the VLSI Design Technology Questions & Answers given below include a hint and wherever possible link to the relevant topic. This is helpful for the users who are preparing for their exams, interviews, or professionals who would like to brush up their fundamentals on the VLSI Design Technology topic. The components like Resistors, Capacitors, Diodes, and Transistors are manufactured separately & these are joined through wires or on a Printed Circuit Board (PCB) to form different circuits which are known as Discrete circuits. For the design of large circuits, more space is needed to accommodate multiple required components, as well as the circuit's reliability, gets affected. To overcome this issue, a circuit with various components are interconnected on a single chip has been developed that is known as an Integrated circuit. Further, the placement of the number of active devices leads to various generations in the IC technology. VLSI is a part of Integrated circuits that paved the way for various applications in the electronic industries like Image and video processing, telecommunications, consumer electronics. 1). VLSI is an acronym for _________________. Very large Scale Integration Varying large Scale Integration Varying large Scale Integrity None of the above Hint 2). Integration circuits possess ______ basic generations. Three Four Five Six Hint 3). Integrated circuit created by VLSI due to the combination of __________ transistors. MOS UJT Diodes Both b & c Hint 4). MOSFETs possess __________. Low packing density High packing density Poor packing density None of the above Hint 5). The circuits integrated are _______ in size. Larger Very large Smaller Bulkier Hint 6). Integrated chip with lesser than 10 transistors is known as _________. Small-scale integration Medium-scale integration Large-scale integration Very large-scale integration Hint 7). How many gates are present on each chip for Medium scale integration? 3-30 30-300 300-3000 None of the above Hint 8). The number of transistors present in LSI are __________. Less than 10 10-100 100-1000 Between 1000-10,000 Hint 9). The classification of ICs is also based on _______. Number of transistors present Presence of the active devices Both a & b None of the above Hint 10). Which circuits work on low voltages? Integrated circuits Discrete circuits Both a and b None of the above Hint 11). More amount of power can be handled by _________ circuits. Integrated Discrete Both a and b None of the above Hint 12). Isolation among the devices is a must in ___________ circuits. Integrated Discrete Both a and b None of the above Hint 13). The adjoining transistors in an integrated circuit can be isolated using ___________ technique. Forward biased PN junction Oxidation Metallization Reverse biased PN junction Hint 14). The initial step involved in the IC fabrication is ___________. Metallization Ion implantation Oxidation Silicon wafer preparation Hint 15). Wafers properties depends upon the ____________ of crystalline structures. Orientation Concentrations of impurity Presence of various impurities All the above Hint 16). The process in which the impurities added to the pure form of silicon is known as ____________. Doping Oxidation Metallization Orientation Hint 17). Heavily doped silicon has _________ resistivity. High Medium Low Ultra high Hint 18). Silicon doped with Boron to obtain _________ substrate. N+ type P+ type N-type P-type Hint 19). The resistivity of the crystal is controlled by the value of _______ added. Dopant Substrate Resistance Capacitance Hint 20). The thickness and the size of the crystal is _________ proportional to each other. Indirectly Inversely Directly None of the above Hint 21) .What is the second step in the IC fabrication? Doping Oxidation Metallization Orientation Hint 22). In silicon the ability of controlling the various impurities and the concentration of doping leads to the formation of _____________________. Diodes Transistors Resistors All the above Hint 23). What are the types of oxidation? Dry oxidation Wet oxidation Both a & b None of the above Hint 24). Deposition of gate oxide prefers _______. Dry oxidation Wet oxidation Both a & b None of the above Hint 25). Masking oxide preparation prefers ___________. Dry oxidation Wet oxidation Both a & b None of the above Hint VLSI Design Technology MCQs for Interview 26). The silicon wafer when reacted with oxygen is converted to _________. Silicon dioxide` Silicon oxide Silica Oxygen Hint 27). Oxidation in silicon can be occurred by raising ______ Pressure Humidity Temperature Volume Hint 28). Sio2 is excellent at ____. Insulating Dielectric Masking All the above Hint 29). The selective removal of oxide from the crystal is known as ___________. Photolithography Oxidation Metallization Orientation Hint 30). Photolithography is all about _____________. Photo resist Masks Radiation All the above Hint 31). For a p-type substrate the diffusion is performed with ___________. P+ N+ Both a & b None of the above Hint 32). What is next step after Photolithography? Oxidation Metallization Orientation Diffusion Hint 33). The diffusion of n+ layer can occur by using _________ dopant. Antimony Arsenic Either a or b Both a & b Hint 34). Growing another layer of crystal on above the top of substrate is known as _______________. Dopant Epitaxy Photo resist Mask Hint 35). The n layer formed due to epitaxy acts as __________ of an npn transistor. Emitter Base Collector Ohmic contact Hint 36). Buried layer diffusion of n+ is performed to reduce _______. Emitter resistance Base resistance Ohmic resistance Collector resistance Hint 37). After all the terminals of the transistor and the ohmic contacts are formed the contact to the outer world is established by ________. Contact metallization Ion implantation Oxidation Diffusion Hint 38). The metal preferred in VLSI for contacting is _________. Antimony Silicon Aluminum Germanium Hint 39). In the advent of the latest technology the contact metal aluminum is replaced with _______. Antimony Silicon Copper Germanium Hint 40). Doping can also be done by using ________. Contact metallization Ion implantation Oxidation Diffusion Hint 41). Field oxide is the first step of fabrication in ___________. BJT UJT MOSFET CMOS Hint 42). The thickness of field oxide in the MOSFET is _________. High Medium Low Ultra high Hint 43). _________ takes active participation performance wise. Field oxide Silicon oxide Gate oxide Substrate Hint 44). What is the most critical step in the fabrication of MOSFETs? Field oxidation Silicon oxidation Gate oxide Wafer preparation Hint 45). MOSFET is a __________ device. Uni-polar Bipolar Complementary Supplementary Hint 46). Types of transistors provided by CMOS technology are ____________. N-type transistors P-type transistors Both a & b Data insufficient Hint 47). Different terminals of the MOS transistors are __________. Source Drain Gate All the above Hint 48).Different types of MOS layers are _______. N-diffusion P-diffusion Polysilicon and metal All the above Hint 49). What are the various modes in the MOSFETs? Enhancement Depletion Both a & b None of the above Hint 50). Enhancement mode MOSFETs are initially _________. Off On Can’t say Fluctuates Hint VLSI Design Technology Question & Answers 51). ___________ MOSFETs are always ON initially. Enhancement Depletion Both a & b None of the above Hint 52). Power is wasted in ________ MOSFETs. Enhancement Depletion Both a & b None of the above Hint 53). For Digital applications ________ is used. 53). For Digital applications ________ is used. Enhancement MOSFETs Depletion MOSFETs Both a & b None of the above Hint 54). Depletion mode n MOSFETs have __________ threshold voltage. Positive Negative Zero Can’t say Hint 55). The threshold voltage of the MOSFET depends upon ________. Thickness of Gate oxide Doping concentration of substrate Variant of metal placed on Gate All the above Hint 56). What are the various types of process in CMOS? P-well and N-well Silicon-On-Insulator Twin-tub All the above Hint 57). The combination of CMOS and the bipolar technologies is ____________. Bi-CMOS Inverter UPS None of the above Hint 58).The various advantages of CMOS process are ____________. Low power dissipation High packing density Offers Bidirectional capabilities All the above Hint 59). Transistors with lesser length of channel i.e., in between 3 to 5 microns are known as _______. Bipolar Unipolar Short channel devices Long channel devices Hint 60). A device in a circuit connected to drag the value of the voltage at output to the lowest supply of voltage is known as ____________. Pull down device Pull up device Short channel device Long channel device Hint 61).Pull up devices can drag the voltage at output to __________. Zero volts Upper supply voltage Lower supply voltage None of the above Hint 62). Which technology is preferred than PMOS? MOS BJT NMOS UJT Hint 63). What are the different regions in which MOS transistors operate? Cut off region Saturated region Non-saturated region All the above Hint 64). ____________ is acts as a interface in between the actual layout and the symbolic circuit. Pie diagrams Venn diagrams Stick diagrams Both a & b Hint 65). Green colour in the stick diagram represents ___________. N-diffusion P-diffusion Polysilicon Contacts Hint 66). Red colour in the stick diagram represents __________. N-diffusion P-diffusion Polysilicon Contacts Hint 67). Buried contact is represented by _____________ colour. Green Red Yellow Brown Hint 68). Contact areas in the stick diagram are represented by ________ colour. Green Black Yellow Brown Hint 69). Increase in the VDS cause growth of ___________at the junction of drain. Majority carriers Minority carriers Depletion region Invalid data Hint 70). Substrate-bias effect is also known as __________. Body effect Bias effect Photo resist Mass effect Hint 71). Threshold voltage in the MOS transistor is applied in between ________ and ______ terminals. Source and Drain Source and Gate Gate and source Gate and Drain Hint 72). Time taken by the waveform to rise initially from ‘10 % to 90%’ of the steady-states value is known as __________. Rise time Fall time Delay time Transient response Hint 73).Time taken by the waveform to fall from ‘90% to 10%’ of the steady-states value is known as _________. Rise time Fall time Delay time Transient response Hint 74).Time taken to pass a logical transition from the input stage to the output is known as ____ Rise time Fall time Delay time Transient response Hint 75).What are the types involved in power dissipation? Dynamic dissipation Static dissipation Both a & b Can’t say Hint VLSI Design Technology Important Questions with Answers 76). Leakage current results in __________ dissipation. Dynamic Static Both a & b Can’t say Hint 77). Dynamic dissipation occurs due to ______. Charging of capacitances at load Discharging of capacitances at load Switching of transient currents All the above Hint 78). CAD in VLSI stands for _______. Computer aided design Computer aided draft Computer animated design Complete aided design Hint 79). BOOM is a ________. Software CAD tool Both a & b None of the above Hint 80). Which is the software used in VLSI? Xilinx Cadence LOON Both a & b Hint 81). ____________ is used in the modeling of digital systems i.e., from algorithmic to switching. C C++ Verilog Java Hint 82). How many types of modeling are present in Verilog? Two Three Four Five Hint 83). What are the various modeling in Verilog? Gate level Data flow Behavioral All the above Hint 84). ___________ modeling describes the usage of logic gates and specifies the way they are wired or connected. Gate level Data flow Behavioral All the above Hint 85). _______________ modeling controls the simulations and manipulates the variables of data types. Gate level Data flow Behavioral All the above Hint 86). In Verilog X represents ___________ condition in the hardware circuits. High impedance Unknown value of logic Logic 1 Logic 0 Hint 87). High impedance and the floating state in Verilog is represented by ______. Z X Y 1 Hint 88). False condition in hardware is represented by ________. Z X 0 1 Hint 89). Level 1 represents ___________ in the hardware circuits. High impedance Unknown value of logic False condition True condition Hint 90). In which phase the micro design of the hardware gets modeled into HDL? RTL coding Placement Routing Post validation Hint 91). The information about the timing of gates is present in ___________-. Register Synthesizer Standard delay file File Hint 92). RTL coding in the VLSI design flow comes under ________ process. Back end Front end Both a & b None of the above Hint 93). Placement and Routing in VLSI comes under ____________ VLSI design. Back end Front end Both a & b None of the above Hint 94). ASIC stands for _________. Application standard of integrated circuits Application-specific intercommunication circuit Application-specific integrated circuit American standard integrated circuit Hint 95). The prefabricated chip of silicon with the most number of transistors has no functions predetermined are known as __________. Gate arrays Registers Uncommitted logic arrays Both a & c Hint 96). How many types of gate arrays are present in ASIC? Three Four Five Six Hint 97). What are the methods of timing control? Delay-based timing control Event-based timing control Level-sensitive timing control All the above Hint 98). Verilog supporting the basic form of logic gates are known as ___________. Predefined primitives Gate arrays ULAs None of the above Hint 99). What are the blocks present in Behavioral modeling? Initial block Always block Both a & b Infinite block Hint 100). Which block gets executed in a particular loop and during simulation gets repeated? Initial block Always block Both a & b Infinite block Hint 101). What are the various types of ASIC? Full custom Semi custom Programmable All the above Hint 102). FPGA classified under _________ ASIC. Full custom Semi custom Programmable All the above Hint 103). Predesigned cells of logic used in a cell based ASIC are known as _____________ Standard cells Primitives Arrays Logic gates Hint 104). EEPROM stands for _________. Electrically Erasable Portable ROM Electrically Erasable Programmable ROM Electrically Erasable Programmable Register of Memory Electrically Eligible Portable Register of Memory Hint 105). Logic cells present in the library of gate arrays are known as _________. Micros Macros Microns Primitives Hint 106). PALs consist of devices that are programmed by altering the switching elements characteristics are known as _______. Macros Antifuse Programmable interconnects Fusible links Hint 107). _____________ tests are used in design cycle as early as possible to verify the circuit functionality. Functionality tests Manufacturing tests Both a & b None of the above Hint 108). ________ tests verify each register and gate functioning properly or not. Functionality tests Manufacturing tests Both a & b None of the above Hint 109). Examples of Fault models __________. Stuck-at faults Short-circuit faults Open-circuit faults All the above Hint 110). The input of a faulty gate modeled to get stuck at zero or stuck at one is possible in ______________. Stuck-at faults Short-circuit faults Open-circuit faults All the above Hint Time is Up! Time's up
