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Direct Memory Access Question & Answers

December 13, 2021 By WatElectronics

This Article lists 100+ Direct Memory Access MCQs for engineering students. All the Direct Memory Access Questions & Answers given below includes solution and link wherever possible to the relevant topic.

The term DMA stands for direct memory access and it is a feature in computer networks. This feature permits particular hardware systems to allow the memory of the main system like RAM separately from the CPU.

Many systems use direct memory access like graphics cards, sound cards, disk drive controllers, network cards, etc. In multi-core processors, direct memory access can also be used for intra chip data transfer.

Computers including DMA channels transfer data from one device to other with very little CPU overhead as compared to computers with no DMA. Likewise, a processing element in a multi-core computer can transmit data to its local memory without using its processor time, allowing calculation & data transfer to continue in parallel.

1). Access to the I/O devices through the peripheral bus is?

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2). DMA transfers data between-------

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3). DMA stands for----?

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4). For transfer of data, devices inform the DMA through------?

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5). DMA acts as------ to the CPU for data transfer.

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6). -------- programs the DMA controller?

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7). DMA controller is connected to---------

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8). DMA controllers vary depending on-------?

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9). The number of I/O devices controlled by DMA depends on---?

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10). Fastest DMA transfer type is------

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11). Fetch and deposit transfer is also known as---?

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12). The---------transfer is more efficient for interfacing devices with different data bus sizes?

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13). Slowest transfer mode of DMA is-----

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14). DMA controller performs multiple DMA transfers in -----mode?

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15). -------determines the number of DMA transfers remaining?

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16). ---------- is useful for performing double buffered data acquisition.

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17). While making network interfaces transfers, DMA makes use of--------------?

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18). When there are no pending valid DMA requests 82C37A enters into------?

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19). The first four states of 82C37A are used for-------?

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20). The DMA controller is programmed using ------------

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21). DREQ is a------------signal.

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22). The controller stops transferring when-----?

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23). After programming, until the DMA request occurs, the controller will be in the----------state?

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24). 8257 DMA controller is a------?

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25). In 8257 DMA the address of the first memory location to be accessed is loaded in------?

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Direct Memory Access Question & Answers for Interviews

26). For each channel 8257 DMA controller has two------registers?

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Please refer to this link for Shift Registers
27). Type of operation of the channel in 8257 is indicated by-------bits of terminal count register?

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28). DMA transfers can cause-----?

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29). To initiate the transfers the processor programs the DMA by sending-----?

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30). While accessing the bus DMA controller is given -----?

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31). ---------has higher reliability.

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32). In-------mode, DMA gives control of buses to CPU after transfer of every byte of data?

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33). Modes of operation in DMA includes….?

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34). Which of the following offers an efficient technique to transfer the information from a device to memory?

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35). Which of the following doesn’t contain a DMA?

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36). Which of the device contains buffer filling with low range?

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37). The DMA controllers depending on the capacity of addressing are….?

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38). In 1D type DMA, how many address registers are there?

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39). A data bus is used to transfer the information from ……to destination?

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40). The bus request from the CPU can be done by using…..?

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41). The signal used to recognize the error within DMA is….?

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42). Which of the following signal allows the DMA to choose the peripheral?

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43). A buffer used by an address mode within DMA for data holding temperorily?

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44). An address stride can be provided by…..model?

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45). The data transfer in DMA can be controlled through….?

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46). Cycle stealing method is used in…?

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47). For which of the following, access time is very faster?

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48). The data transfer within a DMA is ….?

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49). The DMA transfer can be done started through…?

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50). The data transfer mode among the memory & I/O devices is called…?

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Direct Memory Access Question & Answers for Exams

51). The performance of DMA transfer can be done through ……?

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52). In direct memory access transfers, the necessary addresses & signals are provided by the…?

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53). The DMA controller includes….registers?

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54). Which of the following bus is used to connect the controller?

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55). The method where the DMA steals the processor’s access cycles to manage is known as…?

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56). The method which is used by the controller to provide complete access for main memory is?

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57). The DMA controller registers are….?

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58). To reduce the clash on the BUS possession, we use ______?

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59). Which of the following technique avoids the CPU for particular data transfer types?

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60). The technique used for the long distance communication is?

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61). Cycle stealing is used for data transfer based on…?

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62). Which of the following device assists DMA transfer?

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63). How many types of DMA transfer?

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64). The DMA channels numbered in old computers are…?

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65). The 16-bit industry standard architecture introduced ……bus?

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66). The industry standard architecture or ISA is a…?

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67). The data transferred by each DMA per second is?

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68. The system resources are classified into …types?

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69). Types of DMA device?

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70). Host platform DMA are classified into…types?

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71). Components in the DMA software are…types?

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72). The most complex microcontrollers uses ……controller?

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73). How many DMA controllers are there in high density devices?

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74). Which of the following is used to transfer the data from memory to memory, peripheral to peripheral & peripheral to memory?

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75). DMA channels assigned one of …. Priority levels?

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Direct Memory Access Question & Answers for Quiz

76). DMA channel is configured to transmit data into the …. ?

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77). Which of the following is a perfect solution for data stream?

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78). Which of the following accesses only … for transferring actual data?

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79). DMA uses …. Bus cycles to transfer single word between memories?

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80). Every channel in DMA programming can be controlled through?

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81). Registers used in DMA controller programming includes…?

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82). What is DTFR?

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83). What is DMAC?

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84). In DMA mode, how the data transfer can be done…?

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85). In 8257 DMA, very four channels include?

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86). Which of the following pin is used to disable all the DMA channels through removing the mode registers is?

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87). Which of the following pin is used to write data throughout DMA write operation?

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88). The pin that is used to strobe the maximum memory address byte can be generated through the DMA into the latch can be done by?

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89). The DMA controller at a time access how many channels?

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90). DMA controller IC includes….pins?

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91). 8237 DMA IC includes …I/O channels?

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92). The main blocks in the 8237A are?

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93). Which of the following block is used to decode the microprocessor commands given to the DMA?

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Please refer to this link to know more about Microprocessor
94). 8237A operates in … cycles?

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95). In8237A, each cycle includes…states?

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96). Every channel in 8257 IC includes ….registers?

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97). The overload work on the CPU can be decreased by…?

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98). Which of the following problem occurs while DMA transfers the data?

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99). In which of the following IC includes two 16-bit registers

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100). Which of the mode is fastest in DMA

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