Synchronous Counter Question & Answers May 3, 2022 By WatElectronics This article lists 75 Synchronous Counter MCQs for engineering students. All the Synchronous Counter Questions & Answers given below include a hint and a link wherever possible to the relevant topic. This is helpful for users who are preparing for their exams, interviews, or professionals who would like to brush up on their fundamentals on Synchronous Counter. A digital counter is a device designed for counting events happening only on triggers applied. In other terms, these counters operate on the application/input of the clock. They are classified as up-down and down-up counters. These counters are classified into 6 types namely synchronous counter, synchronous decade, asynchronous counter, asynchronous decade, asynchronous up-down counter, and synchronous up-down types. A synchronous type counter also called simultaneous counter is designed using 2 main components J-K flip flop, and AND gates provided with a clock input for each flipflop depending on the bits of the counter. For example, a 3-bit synchronous counter comprises 2 AND logic gates and 3 JK flip flops (ABC) where each is provided with a clock input. Each flip-flop output depends on the input. The disadvantages a synchronous counter overcomes include minimizing operating frequency, propagation delay, and ripple effect. The advantages of a synchronous counter include all the outputs switching simultaneously, each flip flop in a synchronous counter is provided with an individual clock signal and has a high-speed operation. The applications of a synchronous counter include motor RPM counter, rotary shaft encoders, and motor RPM counter. 1). ____ signal in synchronous counter is given as input simultaneously to individual flip-flop. Reset Clock Gnd None of the above Hint 2). Which of the following disadvantages a synchronous counter over comes? Ripple effect Propagation delay Minimizes operating frequency All the above Hint Read more about Ripple Factor. 3). Which of the following are the components of a 3-bit synchronous counter? J-K flip-flops AND gates OR gates Both a and b Hint 4). Which of the following are the flip flops types used for designing synchronous counter? T D JK All the above Hint 5). Which of the following are the advantages of a synchronous counter? All the outputs switch simultaneously Each flip flop in a synchronous counter are provided with individual clock signal High speed All the above Hint 6). Which of the following are the disadvantages of synchronous counter? Additional logic requirement Does not work with clock input Complex design All the above Hint 7). Which of the following are the applications of a synchronous counter? Motor RPM counter Rotary Shaft Encoders All the above Hint 8). Which of the following is the purpose of a counter? Count the event occurrence Store the occurred event Depends on clock signal All the above Hint 9). How many clock inputs does a counter comprises of? 2 3 4 1 Hint 10). How many outputs does a counter comprises of? 1 2 3 Multiple Hint 11). In which of the form does the output of a binary counter is represented in? Binary Binary coded decimal Hexadecimal Both a and b Hint Read more about Decimal Number System 12). Each clock pulse either ___ the number in a counter? Increases Decreases Zero Both a and b Hint 13). A 4-bit synchronous counter starts from ____? 0000 0101 1111 None of the above Hint 14). Which of the following is the stop bit of synchronous counter? 0000 0101 1111 None of the above Hint 15). Which of the following is the output of JK flip-flop when clock = 0 and JK=00? 0 1 X None of the above Hint 16). Which of the following is the output of JK flip-flop when clock = 0 and JK=01? 0 1 X None of the above Hint 17). Which of the following is the output of JK flip-flop when clock = 0 and JK=10? 0 1 X None of the above Hint 18). Which of the following is the output of JK flip-flop when clock = 0 and JK=11? 0 1 X None of the above Hint 19). Which of the following is the output of JK flip-flop when clock = 1 and JK=00? 0 1 X None of the above Hint 20). Which of the following is the output of JK flip-flop when clock = 1 and JK=01? 0 1 X None of the above Hint 21). Which of the following is the output of JK flip-flop when clock = 1 and JK=10? 0 1 X None of the above Hint 22). Which of the following is the output of JK flip-flop when clock = 1 and JK=11? 0 1 X None of the above Hint 23). Which of the following is the output of T-flip flop when Q=’0’ and T=’0’. 0 1 X None of the above Hint 24). Which of the following is the output of T-flip flop when Q=’0’ and T=’1’. 0 1 X None of the above Hint 25). Which of the following is the output of T-flip flop when Q=’1’ and T=’0’. 0 1 X None of the above Hint Synchronous Counter Interview Questions and Answers 26). Which of the following is the output of T-flip flop when Q=’1’ and T=’1’. 0 1 X None of the above Hint 27). How many inputs does a single flip-flop in a synchronous counter comprises of? 2 3 4 5 Hint 28). A BCD type counter has ___ range? 0 to 2^(n) -1 0 to 2(n) -1 0 to 1/2^(n) -1 0 to (n) -1 Hint 29). A standard Binary counter converts data in to which format via additional logic to deploy desired state of sequence? Decimal Hexa Decade binary Both a and c Hint 30). On reaching which of the following term the 4-bit decade synchronous counter resets to ‘0’? 1001 1111 0011 1100 Hint 31). A decade counter is also called ___? Module 9 Module 10 Module 11 Module 13 Hint 32). A synchronous counter uses ___ types of flip-flop to change its state? Edge triggered Positive triggered Negative triggered All the above Hint 33). A positive edge trigger type of flip-flop to change its state is also called ____? Rising edge Falling edge Zero edge None of the above Hint 34). A negative edge trigger type of flip-flop to change its state is also called ____? Rising edge Falling edge Zero edge None of the above Hint 35). In rising edge the logic transaction of a synchronous counter is from ____ point? Low High Zero Constant Hint 36). In rising edge the logic transaction of a synchronous counter raises up to ____? Low High Zero Constant Hint 37). In falling edge the logic transaction of a synchronous counter is from ____ point? Low High Zero Constant Hint 38). In falling edge the logic transaction of a synchronous counter reaches ____ point? Low High Zero Constant Hint 39). One clock cycle is a count of ___? Positive half cycle Negative half cycle Zero half cycle Both a and b Hint 40). Expand MSB in binary system? Most Significant Bit Most Signal Bit Must Significant Bit None of the above Hint 41). Which of the following are the synchronous counter pins used for linking counter? Carry-out Carry-in Sub-in Both a and b Hint 42). Expand LSB? Least Significant Bit Last Significant Bit Least Significant Bit None of the above Hint 43). Which of the following are the types of counter? Synchronous counter Asynchronous counter Synchronous decade All the above Hint 44). Which of the following is the most common type of counters logic circuit? Sequential Combinational Both a and b None of the above Hint 45). A sequential type logic circuit comprises of ______ input pins? 1 2 3 Multiple Hint 46). A sequential type logic circuit comprises of ______ output pins? 1 2 3 Multiple Hint 47). On which of the following term does a synchronous counter depends on for shifting their state? Input clock Output data Mid transition None of the above Hint 48). A synchronous type counter is also called ____? Simultaneous counter Non-simultaneous counter Universal counter Both a and c Hint 49). When input clock applied to synchronous counter is ‘0’ then the flip-flop output is ____? 0 1 Infinite None of the above Hint 50). When input clock applied to synchronous counter is ‘1’ then the flip-flop output is ____? 0 1 Infinite None of the above Hint Synchronous Counter Quiz Questions and Answers. 51). Logic ‘0’ indicates ____? Logic high Logic low Open circuit Both b and c Hint 52). Logic ‘1’ indicates ____? Logic high Logic low Open circuit Both b and c Hint 53). Which of the following output of flip flop out of 3 flip flops (ABC) toggle in a 3-bit synchronous counter at dropping edge condition? A B C None of the above Hint 54). Which of the following output of flip flop out of 3 flip flops (ABC) remain ‘0’ in a 3-bit synchronous counter at dropping edge condition? A B C Both b and c Hint 55). A 3-bit synchronous counter comprises of ____ type of logic gates? AND OR NOT XOR Hint 56). A 3-bit synchronous counter comprises of ____ number of logic AND gate? 2 3 4 5 Hint 57). A 3-bit synchronous counter comprises of ____ type of flip-flop? JK SR T D Hint 58). How many JK flip flops does a 3-bit synchronous counter comprises of ____? 2 3 4 5 Hint 59). To which of the following flip-flop AND gate is connected to in 3-bit synchronous counter? A B C Both a and b Hint 60). The output obtain from flip-flop B in 3-bit synchronous counter depends on flip-flop ___ output? A B C Both a and b Hint 61). When flip-flop A output in 3-bit synchronous counter is high then the flip-flop B output is ____? 0 1 X None of the above Hint 62). Which of the following is the binary form in 3-bit synchronous counter when no clock is given to the circuit? 000 010 111 110 Hint 63). Which of the following is the binary form in 3-bit synchronous counter (CBA) when single clock is given to the circuit flipflop A? 001 010 111 110 Hint 64). Which of the following is the output of AND gate when input is (00)? 0 1 X None of the above Hint 65). Which of the following is the output of AND gate when input is (01)? 0 1 X None of the above Hint Synchronous Counter MCQs for Exams 66). Which of the following is the output of AND gate when input is (10)? 0 1 X None of the above Hint 67). Which of the following is the output of AND gate when input is (11)? 0 1 X None of the above Hint 68). Logic ‘X’ in a logic gates language represents ____? 0 1 00 Either a or b Hint 69). Which of the following scientist discovered flip-flops? FW Jordan William Eccles James Both a and b Hint 70). Which of the following are the first flip-flop circuits? Multivibrators Trigger circuits Schematic trigger All the above Hint 71). Which of the following are used for designing a flip-flop? Logic gates Latches Counters None of the above Hint 72). Which of the following logic gates are used for designing flip-flops? NAND NOR AND Both a and b Hint 73). Which of the following are the applications of flip-flops? Memory Frequency division Registers All the above Hint 74). A register is a collection of ____? Flip-flops Passive elements Active elements None of the above Hint 75). Which of the following are the universal logic gates? AND OR NAND NOT Hint For More MCQs Asynchronous Counter Question & Answers Please fill in the comment box below. Time is Up! Time's up
