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Interrupt Question & Answers

November 22, 2022 By WatElectronics

This article lists 100 Interrupts MCQs for engineering students. All the Interrupts Questions & Answers given below include a hint and a link wherever possible to the relevant topic. This is helpful for users who are preparing for their exams, or interviews, or professionals who would like to brush up on the fundamentals of Interrupts.     

The interrupts are two types software and hardware interrupt. The RST-restart is the software interrupt and RST 6.5, RST 5.5, TRAP, RST 7.5, and INTR are the hardware interrupts. The hardware interrupts are categorized into two they are maskable and non-maskable interrupts. 

The non-maskable interrupts can’t be delayed or rejected but the maskable interrupts can be delayed or rejected. The interrupts can be classified into vectored and non-vectored interrupts. The address of the service routine in vectored interrupt is hard-wired and in non-vectored interrupts, the address of the service routine needs to be supplied extremely by the device. 

The DI interrupt instruction is used to disable the interrupt and the EI interrupt instruction is used to enable the instruction. The DI and EI interrupt instructions both are one-byte instructions. There are two ways to clear TRAP interrupt resetting the microprocessor (external signal) and by giving a high TRAP acknowledgment (internal signal). 

The RST 6.5, RST 5.5, RST 7.5, and INTR interrupts are maskable whereas the TRAP interrupt is not maskable. The RST 6.5, RST 5.5, TRAP, and RST 7.5 are vectored whereas INTR interrupt is not vectored. The RST 6.5, INTR, and RST 5.5 interrupts are level sensitive whereas the RST 7.5 is positive edge sensitive. 

1). Which one of the following is a hardware invoked?

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2). Which one of the following are subset of interrupts?

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3). Which one of the following are asynchronous?

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4). Which one of the following interrupts generated by an input output system?

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5). What is the standard form of PIR?

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6). When interrupt priority enable is zero in global interrupt enable bit the one is equal to _______________?

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7). The vector address of an instruction RST0 is ______________________?

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8). Which one of the following interrupts comes under software interrupt?

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9). The trap comes under __________________ type of interrupt?

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10). What is the standard form of ISR?

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11). The 8085 has ___________________ number of hardware interrupts?

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12). Which one of the following interrupts can be delayed or rejected?

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13). The RST 7.5 maskable interrupt is disabled by _____________________?

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14). What is the standard form of IRQ?

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15). What is the standard form of IPR?

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16). The TF0 is a ___________________ type of interrupt?

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17). What is the address of an external INT 0?

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18). The C7 is the machine HEX code of __________________ instruction?

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19). The vector address of an instruction RST1 is ______________________?

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20). What is the standard form of NMI?

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21). The priority of TRAP interrupt of 8085 is __________________?

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22). The binary equivalent of restart instruction RST 0 is ________________?

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23). Which one of the following is cannot be masked?

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24). Which one of the following interrupts has lowest priority?

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25). What is the standard form of WDT?

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Interrupt MCQ for Exams

26). Which one of the following is a type of branching instruction?

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27). Which one of the following comes under conditional jump instruction?

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28). What is the address of a timer/counter zero?

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29). The INT0 is a ___________________ type of interrupt?

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30). How many types of interrupts are there in MSP430?

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31). Which one of the following are occurs at a well-defined point in the program?

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32). The interrupts are categorized into _______________ types?

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33). The vector address of an instruction RST2 is ______________________?

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34). The binary equivalent of restart instruction RST 1 is ________________?

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35). What is the standard form of PIE?

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36). The priority of RST 7.5 interrupt of 8085 is __________________?

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37). Which one of the following is can be masked?

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38). What is the address of an external interrupt one?

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39). The TF1 is a ___________________ type of interrupt?

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40). What is the standard form of GIE?

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41). Which one of the following interrupts generated by a user program using INT instruction?

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42). The 0018H is a vector address of _____________________ instruction?

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43). The binary equivalent of restart instruction RST 2 is ________________?

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44). The priority of RST 6.5 interrupt of 8085 is __________________?

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45). What is the standard form of BOR?

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46). The JC 2050 is an example for __________________ opcode?

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47). Which one of the following instructions uses a 16-bit address similar to long jump instruction?

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48). How many forms does 8051 provides for the return instruction?

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49). The 0020H is a vector address of _____________________ instruction?

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50). What is the standard form of TAIV?

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Interrupt MCQ for Quiz

51). The binary equivalent of restart instruction RST 7 is ________________?

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52). The JNC 2050 is an example for __________________ opcode?

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53). The TLB miss is an example those caused by an _________________?

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54). The reset button is an example those caused by an _________________?

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55). What is the standard form of PSPIE?

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56). Which one of the following instructions is a two-byte instruction?

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57). How many forms does 8051 provides for the call instruction?

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58). Which one of the following instructions uses an 11-bit address similar to absolute jump instruction?

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59). Which one of the following instructions is a three-byte instruction?

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60). What is the standard form of IVT?

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61). Which one of the following interrupts is vectored?

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62). What is the standard form of ICWs?

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63). The binary equivalent of restart instruction RST 6 is ________________?

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64). The JP 2050 is an example for __________________ opcode?

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65). What is the standard form of ADIE?

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66). Which one of the following is not maskable interrupt?

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67). The command words of 8259 A are classified into ________________ types?

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68). What is the address of a timer/counter one?

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69). The 0028H is a vector address of _____________________ instruction?

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70). Which one of the following is a software invoked?

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71). The call instructions are categorized into __________________ types?

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72). The initialization of stack pointer is not mandatory in __________________ instruction?

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73). In which one of the following instruction the value of stack pointer does not change?

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74). In ______________ instruction, three machine cycles are required to execute the instruction?

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75). What is the standard form of RCIE?

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Interrupt MCQ for Interviews

76). The binary equivalent of restart instruction RST 5 is ________________?

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77). How many machine cycles are required to execute the call instruction?

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78). In which one of the following instruction 10 T states are required to execute the instruction?

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79). The RC is an example for _______________ op-code?

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80). Which one of the following is a single emitted by a hardware device?

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81). Which one of the following instructions is used to enable the interrupt?

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82). The binary equivalent of restart instruction RST 4 is ________________?

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83). In which one of the following instruction the initialization of SP is mandatory?

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84). The priority of INTR interrupt of 8085 is __________________?

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85). What is the standard form of TXIE?

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86). Which one of the following is a BIOS interrupt?

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87). What is the standard form of SFNM?

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88). What is the address of a serial port?

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89). The 0030H is a vector address of _____________________ instruction?

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90). Which one of the following is a single emitted by a user program?

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91). Which one of the following interrupts comes under hardware interrupt?

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92). The priority of RST 5.5 interrupt of 8085 is __________________?

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93). The binary equivalent of restart instruction RST 3 is ________________?

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94). What is the standard form of OCWs?

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95). What is the standard form of TMR1IE?

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96). The RST 6.5 and RST 5.5 maskable interrupts are disabled by __________________?

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97). Which one of the following instructions is used to disable the interrupt?

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98). Which one of the following interrupts cannot be delayed or rejected?

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99). The 0038H is a vector address of _____________________ instruction?

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100). Which one of the following are superset of traps?

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