ARM Architecture Question & Answers October 11, 2021 By WatElectronics This article lists 100 ARM Architecture MCQs for Engineering Students. All the ARM Architecture Questions & Answers given below includes solution and link wherever possible to the relevant topic. The ARM processor is one of the families of CPUs, which is based on the RISC architecture. The CPU can have two types of architecture they are RISC and CISC architecture. In RISC architectures the number of instructions involves is less and the instructions are also very simple, whereas in CISC architectures the number of instructions involves is more and the instructions are also very complex. The standard form of ARM is Advanced RISC Machine, it has three instruction sets they are 32-bit ARM, 16-bit Thumb, and 8-bit Jazelle instruction set. It has 37 registers, 1 is a dedicated program counter, 1 is a current program status register, 5 saved program status registers, and 30 are general-purpose registers, and has seven basic operating modes they are user, FIQ, IRQ, supervisor, un-def, and system. When the processor is executing in ARM state, then all instructions are 32-bits wide. The ARM has two arithmetic shift operators they are arithmetic shift right and arithmetic shift left. The load instructions are categorized into three types they are multiple register transfer, single register transfer, and swap. The FIQ, IRQ, SVC, USR, ABT, UND are the hardware stacks in ARM7/9. The ARM and thumb instruction set and java byte codes are Jazelle instruction sets. The ARM MMU architecture translates virtual addresses into physical addresses and controls the memory access permissions function. The ARM instruction set architecture is divided into six classes of instructions they are data processing, branch, status register transfer, load & store, co-processor, and exception generating instructions. The RISC, ISA optimization, application-specific components are the power-saving techniques for ARM CPUs. The load and store, data processing, branch, and coprocessor are the ARM instruction sets. 1). What is the standard form of ARM? Advanced RISC Machine Automatic RISC Machine Automatic RISC Motor None of the above None Hint 2). How many instruction sets does ARM have? One Two Three Four None Hint 3). How many registers does ARM have? Four Eight Sixteen Thirty-seven None Hint 4). How many operating modes does ARM have? Four Seven Sixteen Thirty-seven None Hint 5). When the processor is executing in ARM state, then all instructions are ______________ wide 8-bits 16-bits 32-bits 64-bits None Hint 6). What is the standard form of LSL? Logical Shift Left Left Shift Logical Logical Shift Logic None of the above None Hint 7). How many arithmetic shift operators does ARM have? One Two Three Four None Hint 8). How many types of load instructions are there? One Two Three Four None Hint 9). How many classes of hazards are there? One Two Three Four None Hint 10). The OS timer is external peripheral in _____________ ARM7/9 Cortex-M3 Both a and b None of the above None Hint 11). __________________ are the hardware stacks in ARM7/9 FIQ, IRQ SVC, USR ABT, UND All of the above None Hint 12). Which one of the following architecture has fewer number instructions? RISC CISC Both a and b None of the above None Hint 13). In which one of the following architecture the instructions are simple? RISC CISC Both a and b None of the above None Hint 14). The RISC processors execute ______________ of instructions per second Hundred Thousands Millions None of the above None Hint 15). Which one of the following is a CISC architecture? ARM7 8051 Both a and b None of the above None Hint Read more about CISC Architecture 16). When the processor is executing in thumb state, then all instructions are ______________ wide 8-bits 16-bits 32-bits 64-bits None Hint 17). Which one of the following executes all instructions in one cycle? ARM7 8051 Both a and b None of the above None Hint 18). What is the standard form of LSR? Logical Shift Right Left Shift Right Local Shift Right None of the above None Hint 19). Which one of the following is the 8-bit controller? ARM7 8051 Both a and b None of the above None Hint 20). The ARM instruction set architecture divided into __________ classes of instructions Two Four Six Eight None Hint Read more about ARM Processor 21). What is the standard form of LPAE? Large Page Address Extensions Large Page Automatic Extensions Large Page ARM Extensions None of the above None Hint 22). _____________ are the power saving techniques for ARM CPU’s RISC ISA optimization Application-specific components All of the above None Hint 23). When the processor is executing in jazelle state, then all instructions are ______________ wide 8-bits 16-bits 32-bits 64-bits None Hint 24). What is the standard form of ASR? Automatic Shift Right ARM Shift Right Arithmetic Shift Right None of the above None Hint 25). What is the standard form of AMULET? Asynchronous Microprocessor Using Low Energy Technology Automatic Microprocessor Using Low Energy Technology ARM Microprocessor Using Low Energy Technology None of the above None Hint ARM Architecture Important MCQ’s 26). The frequency of load/store instruction is around _________ 20% 10% 40% 67% None Hint 27). In which year cortex R4 processor is introduced? 2005 2010 2012 2016 None Hint 28). What is the standard form of ADK? ARM Design Kit Advanced Design Kit AMBA Design Kit None of the above None Hint 29). The branch with link, software interrupt, and general branch instructions are the _______________ instructions Branch Data processing ARM None of the above None Hint 30). The typical clock rate of ARM9E is around ______________ 100 MHZ (130nm) 335 MHZ (130nm) 266 MHZ (130nm) None of the above None Hint 31). The advanced RISC machine processors supports ____________ bytes 8-bit signed & unsigned 16-bit signed & unsigned 32-bit signed & unsigned All of the above None Hint 32). What are the benefits of on-chip RAM? Simpler Cheaper Uses less power All of the above None Hint 33). What is the standard form of ASL? Automatic Shift Left ARM Shift Left Arithmetic Shift Left None of the above None Hint 34). The frequency of fix and float instruction is around _________ 2% 10% 40% 67% None Hint 35). What is the standard form of NVIC? Nested Vectored Internal Controller Nested Vectored Interface Controller Nested Vectored Interrupt Controller None of the above None Hint 36). What is the standard form of CPSR? Current Program Register Current Program Status Register Complex Program Register None of the above None Hint 37). In which year cortex R5 processor is introduced? 2005 2010 2012 2016 None Hint 38). What is the standard form of CPI? Cycles Per Instructions Complex Cycles Per Instructions Current Per Instructions None of the above None Hint 39). The load and store, data processing, branch, and coprocessor are the ___________ instruction set Branch Data processing ARM None of the above None Hint 40). What is the standard form of BTRAN? Bus Transfer Bus Transistor Bus Transaction None of the above None Hint 41). The typical die size of ARM7TDMI is around __________ 10 mm^2 20 mm^2 0.53 mm^2 None of the above None Hint 42). What is the standard form of FPE? Floating Point Emulator Floating Pan Emulator Floating Programmable Emulator None of the above None Hint 43). In which year cortex R7 processor is introduced? 2005 2010 2012 2016 None Hint 44). What is the standard form of TCM? Tightly Coupled Memory Tightly Controller Memory Tightly Coupled Microprocessor None of the above None Hint 45). What is the standard form of MMU? Memory Management Unit Map Management Unit Management Memory Unit None of the above None Hint 46). The directly executed byte codes, emulated byte codes, and undefined byte codes are the _____________ byte codes Java Jazelle ARM None of the above None Hint 47). What is the standard form of FPASC? Floating Point Accumulator Support Code Floating Point Accelerator Support Code Floating Point ARM Support Code None of the above None Hint 48). The ARM and thumb instruction set and java byte codes are ___________ instruction set Java Jazelle ARM None of the above None Hint 49). Which one of the following is the coprocessor instructions? Data processing, register transfer, and data transfer instructions Load or store single register, load and store multiple register Multiply instructions, status register transfer instructions None of the above None Hint 50). The typical clock rate of ARM11 is around ______________ 100 MHZ (130nm) 335 MHZ (130nm) 266 MHZ (130nm) None of the above None Hint ARM Architecture MCQ’s for Quiz 51). What is the standard form of CLZ? Count Leading Zeros Complex Leading Zeros Control Leading Zeros None of the above None Hint 52). The typical die size of ARM720T is around __________ 10 mm^2 2.93 mm^2 0.53 mm^2 None of the above None Hint 53). What is the standard form of LRU? Least Recently Used Lower Recently Used Larger Recently Used None of the above None Hint 54). The clock speed of ARM7TDMI is around ___________ 10-20 MHz 20-30 MHz 50-60 MHz 80-100 MHz None Hint 55). The program status register combines _______________ registers APSR IPSR EPSR All of the above None Hint 56). What is the standard form of EPLD? Electrically Programmable Large Device Electrically Programmable Logic Device Electrically Point Large Device None of the above None Hint 57). Which one of the following is the load and store instructions? Data processing, register transfer, and data transfer instructions Load or store single register, load and store multiple register Multiply instructions, status register transfer instructions None of the above None Hint 58). The typical die size of ARM920T is around __________ 10 mm^2 2.93 mm^2 0.53 mm^2 11.8 mm^2 None Hint 59). The typical clock rate of cortex R4 is around ______________ 100 MHZ (130nm) 335 MHZ (130nm) 376 MHZ (90nm) None of the above None Hint 60). What is the standard form of AMBA? ARM Microcontroller Bus Architecture Advanced Microcontroller Bus Architecture ARM Microprocessor Bus Architecture None of the above None Hint 61). The typical die size of ARM926EJ-S is around __________ 10 mm^2 2.93 mm^2 3.5 mm^2 11.8 mm^2 None Hint 62). How much power does the ARM7TDMI core consume? 10 mW/MHz 0.25 mW/MHz 20 mW/MHz 40 mW/MHz None Hint 63). The clock speed of ARM720T is between ___________ 10-20 MHz 20-30 MHz 60-75 MHz 80-100 MHz None Hint 64). What is the standard form of FPA? Floating Point Accelerator Floating Point ARM Floating Point Application None of the above None Hint 65). Which one of the following is the data processing instructions? Data processing, register transfer, and data transfer instructions Load or store single register, load and store multiple register Multiply instructions, status register transfer instructions None of the above None Hint 66). What is the standard form of APSR? Application Program Status Register ARM Program Status Register Advanced Program Status Register None of the above None Hint 67). What is the standard form of ICACHE? Instruction Cache Interrupt Cache Information Cache None of the above None Hint 68). How much power does the ARM720T core consume? 10 mW/MHz 0.65 mW/MHz 20 mW/MHz 40 mW/MHz None Hint 69). What is the standard form of ASSP? Application-Specific Standard Pan Advanced Specific Standard Procedure ARM Specific Standard Procedure None of the above None Hint 70). The clock speed of ARM920T is around ___________ 10-20 MHz 20-30 MHz 60-75 MHz 220 MHz None Hint 71). What is the standard form of IPSR? Internal Program Status Register Interference Program Status Register Interrupt Program Status Register None of the above None Hint 72). What is the standard form of CAM? Content ARM Memory Content Addressable Memory Content Advanced Memory None of the above None Hint 73). How much power does the ARM920T core consume? 10 mW/MHz 0.8 mW/MHz 20 mW/MHz 40 mW/MHz None Hint 74). The access control is based on ___________ sort of programs Clients Managers Both a and b None of the above None Hint 75). The ARM MMU architecture performs ________________ function Translates virtual addresses into physical addresses Controls memory access permissions Both a and b None of the above None Hint ARM Architecture Important MCQ’s for Exams 76). Which one of the following architecture has more number instructions? RISC CISC Both a and b None of the above None Hint 77). What is the standard form of VRAM? Video Random Access Memory Virtual Random Access Memory Video/Virtual Random Access Memory None of the above None Hint 78). What is the standard form of APCS? Asynchronous Procedure Call Standard Automatic Procedure Call Standard ARM Procedure Call Standard None of the above None Hint 79). The typical clock rate of cortex A8 w/NEON is around ______________ 100 MHZ (130nm) 335 MHZ (130nm) 376 MHZ (90nm) 450 MHA-1100MHZ(65nm) None Hint 80). How much power does the ARM926EJ-S core consume? 10 mW/MHz 1.8 mW/MHz 20 mW/MHz 40 mW/MHz None Hint 81). The clock speed of ARM926EJ-S is between ___________ 10-20 MHz 180-270 MHz 60-75 MHz 220 MHz None Hint 82). What is the standard form of TLB? Transistor Look Aside Buffer Translation Look Aside Buffer Transformer Look Aside Buffer None of the above None Hint 83). What is the standard form of EPSR? External Program Status Register Execution Program Status Register Emulator Program Status Register None of the above None Hint 84). Which one of the following is a cache write strategy? Write-through Copy back Write through with buffered write All of the above None Hint 85). What is the standard form of SPSR? Synchronous Program Status Register Asynchronous Program Status Register Saved Program Status Register None of the above None Hint 86). _______________ cycles are the basic types of memory cycle Idle cycle Sequential & non-sequential cycle En-processor register cycle All of the above None Hint 87). Which one of the following cycles doesn’t require a transfer? Idle cycle Sequential & non-sequential cycle Internal cycle All of the above None Hint 88). What is the standard form of SDLC? Synchronous Digital Logic Controller Synchronous Data Link Controller Saved Digital Logic Controller None of the above None Hint 89). Which one of the following is a syntax for comparison instruction? {}{S} Rd, N {}{S} Rd, Rn, N {}Rn, N None of the above None Hint 90). Which one of the following is a syntax for software interrupt instruction? SWI{} SWI_number SWI{} SWI_number None of the above None Hint 91). Which one of the following is a syntax for logical instruction? {}{S} Rd, N {}{S} Rd, Rn, N {}Rn, N None of the above None Hint 92). What is the standard form of FSM? Finite Set Machine Finite Status Machine Float Set Machine None of the above None Hint 93). Which one of the following is a syntax for MOV instruction? {}{S} Rd, N {}{S} Rd, Rn, N {}{S} Rn, N None of the above None Hint 94). The clock speed of ARM1020E is around ___________ 10-20 MHz 20-30 MHz 50-60 MHz 400 MHz None Hint 95). In which one of the following architecture the instructions are complex? RISC CISC Both a and b None of the above None Hint 96). How many types of load-store instructions are there? One Two Three Four None Hint 97). What is the standard form of ACT? ARM controller Test bench Advanced controller Test bench AMBA Compliance Test bench None of the above None Hint 98). How many types of pipeline hazards are there? One Two Three Four None Hint 99). What is the standard form of DCACHE? Data Cache Dynamic Cache Data/Dynamic cache None of the above None Hint 100). What is the standard form of FPSR? Floating Point Set Register Finite Point Set Register Floating Point Status Register None of the above None Hint Time's up
