ARM Architecture Question & AnswersOctober 11, 2021 By WatElectronics This article lists 100 ARM Architecture MCQs for Engineering Students. All the ARM Architecture Questions & Answers given below includes solution and link wherever possible to the relevant topic.The ARM processor is one of the families of CPUs, which is based on the RISC architecture. The CPU can have two types of architecture they are RISC and CISC architecture. In RISC architectures the number of instructions involves is less and the instructions are also very simple, whereas in CISC architectures the number of instructions involves is more and the instructions are also very complex 1). What is the standard form of ARM?Advanced RISC MachineAutomatic RISC MachineAutomatic RISC MotorNone of the aboveHintThe standard form of ARM is Advanced RISC Machine 2). How many instruction sets does ARM have?OneTwoThreeFourHintThe ARM has three instruction sets they are 32-bit ARM, 16-bit Thumb, and 8-bit jazelle instruction set 3). How many registers does ARM have?FourEightSixteenThirty-sevenHintThe Advanced RISC Machine has 37 registers, 1 is a dedicated program counter, 1 is current program status register, 5 saved program status registers, and 30 are general-purpose registers 4). How many operating modes does ARM have?FourSevenSixteenThirty-sevenHintThe ARM has seven basic operating modes they are user, FIQ, IRQ, supervisor, abort, un-def, and system 5). When the processor is executing in ARM state, then all instructions are ______________ wide8-bits16-bits32-bits64-bitsHintWhen the processor is executing in ARM state, then all instructions are 32-bits wide 6). What is the standard form of LSL?Logical Shift LeftLeft Shift LogicalLogical Shift LogicNone of the aboveHintThe standard form of LSL is Logical Shift Left 7). How many arithmetic shift operators does ARM have?OneTwoThreeFourHintThe ARM has two arithmetic shift operators they are arithmetic shift right and arithmetic shift left 8). How many types of load instructions are there?OneTwoThreeFourHintThe load instructions are categorized into three types they are multiple register transfer, single register transfer, and swap 9). How many classes of hazards are there?OneTwoThreeFourHintThere are three classes of hazards they are structural hazards, data hazards, and control hazards 10). The OS timer is external peripheral in _____________ARM7/9Cortex-M3Both a and bNone of the aboveHintThe OS timer is external peripheral in ARM7/9 11). __________________ are the hardware stacks in ARM7/9FIQ, IRQSVC, USRABT, UNDAll of the aboveHintThe FIQ, IRQ, SVC, USR, ABT, UND are the hardware stacks in ARM7/9 12). Which one of the following architecture has fewer number instructions?RISCCISCBoth a and bNone of the aboveHintThe reduced instruction set computer have less number of instructions 13). In which one of the following architecture the instructions are simple?RISCCISCBoth a and bNone of the aboveHintThe reduced instruction set computer architecture the instructions are simple 14). The RISC processors execute ______________ of instructions per secondHundredThousandsMillionsNone of the aboveHintThe RISC processors execute millions of instructions per second 15). Which one of the following is a CISC architecture?ARM78051Both a and bNone of the aboveHintThe 8051 is a complex instruction set computer architecture Read more about CISC Architecture 16). When the processor is executing in thumb state, then all instructions are ______________ wide8-bits16-bits32-bits64-bitsHintWhen the processor is executing in thumb state, then all instructions are 16-bits wide 17). Which one of the following executes all instructions in one cycle?ARM78051Both a and bNone of the aboveHintThe ARM7 executes all instructions in one cycle 18). What is the standard form of LSR?Logical Shift RightLeft Shift RightLocal Shift RightNone of the aboveHintThe standard form of LSR is Logical Shift Right 19). Which one of the following is the 8-bit controller?ARM78051Both a and bNone of the aboveHintThe 8051 is the eight-bit controller 20). The ARM instruction set architecture divided into __________ classes of instructionsTwoFourSixEightHintThe ARM instruction set architecture is divided into six classes of instructions they are data processing, branch, status register transfer, load & store, co-processor, and exception generating instructions Read more about ARM Processor 21). What is the standard form of LPAE?Large Page Address ExtensionsLarge Page Automatic ExtensionsLarge Page ARM ExtensionsNone of the aboveHintThe standard form of LPAE is Large Page Address Extensions 22). _____________ are the power saving techniques for ARM CPU’sRISCISA optimizationApplication-specific componentsAll of the aboveHintThe RISC, ISA optimization, application-specific components are the power saving techniques for ARM CPU’s 23). When the processor is executing in jazelle state, then all instructions are ______________ wide8-bits16-bits32-bits64-bitsHintWhen the processor is executing in jazelle state, then all instructions are 8-bits wide 24). What is the standard form of ASR?Automatic Shift RightARM Shift RightArithmetic Shift RightNone of the aboveHintThe standard form of ASR is Arithmetic Shift Right 25). What is the standard form of AMULET?Asynchronous Microprocessor Using Low Energy TechnologyAutomatic Microprocessor Using Low Energy TechnologyARM Microprocessor Using Low Energy TechnologyNone of the aboveHintThe standard form of AMULET is Asynchronous Microprocessor Using Low Energy TechnologyARM Architecture Important MCQ’s 26). The frequency of load/store instruction is around _________20%10%40%67%HintThe frequency of load/store instruction is around 67% 27). In which year cortex R4 processor is introduced?2005201020122016HintIn 2005 cortex R4 processor is introduced 28). What is the standard form of ADK?ARM Design KitAdvanced Design KitAMBA Design KitNone of the aboveHintThe standard form of ADK is AMBA Design Kit 29). The branch with link, software interrupt, and general branch instructions are the _______________ instructionsBranchData processingARMNone of the aboveHintThe branch with the link, software interrupt, and general branch instructions are the branch instructions 30). The typical clock rate of ARM9E is around ______________100 MHZ (130nm)335 MHZ (130nm)266 MHZ (130nm)None of the aboveHintThe typical clock rate of ARM9E is around 266 MHZ (130nm) 31). The advanced RISC machine processors supports ____________ bytes8-bit signed & unsigned16-bit signed & unsigned32-bit signed & unsignedAll of the aboveHintThe advanced RISC machine processors support 8-bit, 16-bit, 32-bit signed & unsigned bytes 32). What are the benefits of on-chip RAM?SimplerCheaperUses less powerAll of the aboveHintThe benefits of on-chip RAM are they are simpler, cheaper, and uses less power 33). What is the standard form of ASL?Automatic Shift LeftARM Shift LeftArithmetic Shift LeftNone of the aboveHintThe standard form of ASL is Arithmetic Shift Left 34). The frequency of fix and float instruction is around _________2%10%40%67%HintThe frequency of fix and float instruction is around 2% 35). What is the standard form of NVIC?Nested Vectored Internal ControllerNested Vectored Interface ControllerNested Vectored Interrupt ControllerNone of the aboveHintThe standard form of NVIC is Nested Vectored Interrupt Controller 36). What is the standard form of CPSR?Current Program RegisterCurrent Program Status RegisterComplex Program RegisterNone of the aboveHintThe standard form of CPSR is Current Program Status Register 37). In which year cortex R5 processor is introduced?2005201020122016HintIn 2010 cortex R5 processor is introduced 38). What is the standard form of CPI?Cycles Per InstructionsComplex Cycles Per InstructionsCurrent Per InstructionsNone of the aboveHintThe standard form of CPI is Cycles Per Instructions 39). The load and store, data processing, branch, and coprocessor are the ___________ instruction setBranchData processingARMNone of the aboveHintThe load and store, data processing, branch, and coprocessor are the ARM instruction set 40). What is the standard form of BTRAN?Bus TransferBus TransistorBus TransactionNone of the aboveHintThe standard form of BTRAN is Bus Transaction 41). The typical die size of ARM7TDMI is around __________10 mm^220 mm^20.53 mm^2None of the aboveHintThe typical die size of ARM7TDMI is around 0.53 mm^2 42). What is the standard form of FPE?Floating Point EmulatorFloating Pan EmulatorFloating Programmable EmulatorNone of the aboveHintThe standard form of FPE is the standard form of FPE 43). In which year cortex R7 processor is introduced?2005201020122016HintIn 2012 cortex R7 processor is introduced 44). What is the standard form of TCM?Tightly Coupled MemoryTightly Controller MemoryTightly Coupled MicroprocessorNone of the aboveHintThe standard form of TCM is Tightly Coupled Memory 45). What is the standard form of MMU?Memory Management UnitMap Management UnitManagement Memory UnitNone of the aboveHintThe standard form of MMU is Memory Management Unit 46). The directly executed byte codes, emulated byte codes, and undefined byte codes are the _____________ byte codesJavaJazelleARMNone of the aboveHintThe directly executed byte codes, emulated byte codes, and undefined byte codes are the java byte codes 47). What is the standard form of FPASC?Floating Point Accumulator Support CodeFloating Point Accelerator Support CodeFloating Point ARM Support CodeNone of the aboveHintThe standard form of FPASC is Floating Point Accelerator Support Code 48). The ARM and thumb instruction set and java byte codes are ___________ instruction setJavaJazelleARMNone of the aboveHintThe ARM and thumb instruction set and java byte codes are jazelle instruction set 49). Which one of the following is the coprocessor instructions?Data processing, register transfer, and data transfer instructionsLoad or store single register, load and store multiple registerMultiply instructions, status register transfer instructionsNone of the aboveHintThe data processing, register transfer, and data transfer instructions are the coprocessor instructions 50). The typical clock rate of ARM11 is around ______________100 MHZ (130nm)335 MHZ (130nm)266 MHZ (130nm)None of the aboveHintThe typical clock rate of ARM11 is around 335 MHZ (130nm)ARM Architecture MCQ’s for Quiz 51). What is the standard form of CLZ?Count Leading ZerosComplex Leading ZerosControl Leading ZerosNone of the aboveHintThe standard form of CLZ is Count Leading Zeros 52). The typical die size of ARM720T is around __________10 mm^22.93 mm^20.53 mm^2None of the aboveHintThe typical die size of ARM720T is around 2.93 mm^2 53). What is the standard form of LRU?Least Recently UsedLower Recently UsedLarger Recently UsedNone of the aboveHintThe standard form of LRU is Least Recently Used 54). The clock speed of ARM7TDMI is around ___________10-20 MHz20-30 MHz50-60 MHz80-100 MHzHintThe clock speed of ARM7TDMI is between 80-100 MHz 55). The program status register combines _______________ registersAPSRIPSREPSRAll of the aboveHintThe program status register combines APSR, IPSR, and EPSR registers 56). What is the standard form of EPLD?Electrically Programmable Large DeviceElectrically Programmable Logic DeviceElectrically Point Large DeviceNone of the aboveHintThe standard form of EPLD is Electrically Programmable Logic Device 57). Which one of the following is the load and store instructions?Data processing, register transfer, and data transfer instructionsLoad or store single register, load and store multiple registerMultiply instructions, status register transfer instructionsNone of the aboveHintThe load or store single register, load and store multiple registers are the load and store instructions 58). The typical die size of ARM920T is around __________10 mm^22.93 mm^20.53 mm^211.8 mm^2HintThe typical die size of ARM920T is around 11.8 mm^2 59). The typical clock rate of cortex R4 is around ______________100 MHZ (130nm)335 MHZ (130nm)376 MHZ (90nm)None of the aboveHintThe typical clock rate of cortex R4 is around 376 MHZ (90nm) 60). What is the standard form of AMBA?ARM Microcontroller Bus ArchitectureAdvanced Microcontroller Bus ArchitectureARM Microprocessor Bus ArchitectureNone of the aboveHintThe standard form of AMBA is Advanced Microcontroller Bus Architecture 61). The typical die size of ARM926EJ-S is around __________10 mm^22.93 mm^23.5 mm^211.8 mm^2HintThe typical die size of ARM926EJ-S is around 3.5 mm^2 62). How much power does the ARM7TDMI core consume?10 mW/MHz0.25 mW/MHz20 mW/MHz40 mW/MHzHintThe ARM7TDMI core consumes0.25 mW/MHz power 63). The clock speed of ARM720T is between ___________10-20 MHz20-30 MHz60-75 MHz80-100 MHzHintThe clock speed of ARM720T is between 60-75 MHz 64). What is the standard form of FPA?Floating Point AcceleratorFloating Point ARMFloating Point ApplicationNone of the aboveHintThe standard form of FPA is Floating Point Accelerator 65). Which one of the following is the data processing instructions?Data processing, register transfer, and data transfer instructionsLoad or store single register, load and store multiple registerMultiply instructions, status register transfer instructionsNone of the aboveHintThe multiply instructions, status register transfer instructions are the data processing instructions 66). What is the standard form of APSR?Application Program Status RegisterARM Program Status RegisterAdvanced Program Status RegisterNone of the aboveHintThe standard form of APSR is Application Program Status Register 67). What is the standard form of ICACHE?Instruction CacheInterrupt CacheInformation CacheNone of the aboveHintThe standard form of ICACHE is instruction Cache 68). How much power does the ARM720T core consume?10 mW/MHz0.65 mW/MHz20 mW/MHz40 mW/MHzHintThe ARM720T core consumes0. 65 mW/MHz power 69). What is the standard form of ASSP?Application-Specific Standard PanAdvanced Specific Standard ProcedureARM Specific Standard ProcedureNone of the aboveHintThe standard form of ASSP is Application Specific Standard Pan 70). The clock speed of ARM920T is around ___________10-20 MHz20-30 MHz60-75 MHz220 MHzHintThe clock speed of ARM920T is around 220 MHz 71). What is the standard form of IPSR?Internal Program Status RegisterInterference Program Status RegisterInterrupt Program Status RegisterNone of the aboveHintThe standard form of IPSR is Interrupt Program Status Register 72). What is the standard form of CAM?Content ARM MemoryContent Addressable MemoryContent Advanced MemoryNone of the aboveHintThe standard form of CAM is Content Addressable Memory 73). How much power does the ARM920T core consume?10 mW/MHz0.8 mW/MHz20 mW/MHz40 mW/MHzHintThe ARM920T core consumes 0. 8 mW/MHz power 74). The access control is based on ___________ sort of programsClientsManagersBoth a and bNone of the aboveHintThe access control is based on clients and managers sort of programs 75). The ARM MMU architecture performs ________________ functionTranslates virtual addresses into physical addressesControls memory access permissionsBoth a and bNone of the aboveHintThe ARM MMU architecture translates virtual addresses into physical addresses and controls the memory access permissions functionARM Architecture Important MCQ’s for Exams 76). Which one of the following architecture has more number instructions?RISCCISCBoth a and bNone of the aboveHintThe complex instruction set computer has more number instructions 77). What is the standard form of VRAM?Video Random Access MemoryVirtual Random Access MemoryVideo/Virtual Random Access MemoryNone of the aboveHintThe standard form of VRAM is Video Random Access Memory 78). What is the standard form of APCS?Asynchronous Procedure Call StandardAutomatic Procedure Call StandardARM Procedure Call StandardNone of the aboveHintThe standard form of APCS is ARM Procedure Call Standard 79). The typical clock rate of cortex A8 w/NEON is around ______________100 MHZ (130nm)335 MHZ (130nm)376 MHZ (90nm)450 MHA-1100MHZ(65nm)HintThe typical clock rate of cortex A8 w/NEON is around 450 MHA-1100MHZ(65nm) 80). How much power does the ARM926EJ-S core consume?10 mW/MHz1.8 mW/MHz20 mW/MHz40 mW/MHzHintThe ARM926EJ-S core consumes 1. 8 mW/MHz power 81). The clock speed of ARM926EJ-S is between ___________10-20 MHz180-270 MHz60-75 MHz220 MHzHintThe clock speed of ARM926EJ-S is between 180-270 MHz 82). What is the standard form of TLB?Transistor Look Aside BufferTranslation Look Aside BufferTransformer Look Aside BufferNone of the aboveHintThe standard form of TLB is Translation Look Aside Buffer 83). What is the standard form of EPSR?External Program Status RegisterExecution Program Status RegisterEmulator Program Status RegisterNone of the aboveHintThe standard form of EPSR is Execution Program Status Register 84). Which one of the following is a cache write strategy?Write-throughCopy backWrite through with buffered writeAll of the aboveHintThe write-through, copy back, and write through with buffered write are the cache write strategies 85). What is the standard form of SPSR?Synchronous Program Status RegisterAsynchronous Program Status RegisterSaved Program Status RegisterNone of the aboveHintThe standard form of SPSR is Saved Program Status Register 86). _______________ cycles are the basic types of memory cycleIdle cycleSequential & non-sequential cycleEn-processor register cycleAll of the aboveHintThe idle, sequential & non-sequential cycle, en-processor register cycles are the basic types of the memory cycle 87). Which one of the following cycles doesn’t require a transfer?Idle cycleSequential & non-sequential cycleInternal cycleAll of the aboveHintThe internal cycle doesn’t require a transfer 88). What is the standard form of SDLC?Synchronous Digital Logic ControllerSynchronous Data Link ControllerSaved Digital Logic ControllerNone of the aboveHintThe standard form of SDLC is Synchronous Data Link Controller 89). Which one of the following is a syntax for comparison instruction?{}{S} Rd, N{}{S} Rd, Rn, N{}Rn, NNone of the aboveHintThe syntax for comparison instruction is {}Rn, N 90). Which one of the following is a syntax for software interrupt instruction?SWI{} SWI_numberSWI{}SWI_numberNone of the aboveHintThe syntax for software interrupt instruction is SWI{} SWI_number 91). Which one of the following is a syntax for logical instruction?{}{S} Rd, N{}{S} Rd, Rn, N{}Rn, NNone of the aboveHintThe syntax for logical instruction is {}{S} Rd, Rn, N 92). What is the standard form of FSM?Finite Set MachineFinite Status MachineFloat Set MachineNone of the aboveHintThe standard form of FSM is Finite Status Machine 93). Which one of the following is a syntax for MOV instruction?{}{S} Rd, N{}{S} Rd, Rn, N{}{S} Rn, NNone of the aboveHintThe syntax for MOV instruction is {}{S} Rd, N 94). The clock speed of ARM1020E is around ___________10-20 MHz20-30 MHz50-60 MHz400 MHzHintThe clock speed of ARM7TDMI is around 400 MHz 95). In which one of the following architecture the instructions are complex?RISCCISCBoth a and bNone of the aboveHintThe complex instruction set computer architecture the instructions are complex 96). How many types of load-store instructions are there?OneTwoThreeFourHintThe load-store instructions are of three types they are single register transfer, multiple register transfer, and swap instruction 97). What is the standard form of ACT?ARM controller Test benchAdvanced controller Test benchAMBA Compliance Test benchNone of the aboveHintThe standard form of ACT is the AMBA Compliance Test bench 98). How many types of pipeline hazards are there?OneTwoThreeFourHintThere are three types of pipeline hazards are there they are structural, data, and control hazards 99). What is the standard form of DCACHE?Data CacheDynamic CacheData/Dynamic cacheNone of the aboveHintThe standard form of DCACHE is Data Cache 100). What is the standard form of FPSR?Floating Point Set RegisterFinite Point Set RegisterFloating Point Status RegisterNone of the aboveHintThe standard form of FPSR is Floating-Point Status Register Time is Up! Time's up
